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DOE OSTI · 1163975

Store-operate-coherence-on-value

Chen, Dong·Heidelberger, Philip·Kumar, Sameer·Ohmacht, Martin·Steinmacher-Burow, Burkhard
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Abstract

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

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Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, Steinmacher-Burow, Burkhard. 2014-11-18. Store-operate-coherence-on-value. https://www.osti.gov/biblio/1163975

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