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DOE OSTI · 1422725

Low power adaptive synchronizer

Sadowski, Greg
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Abstract

A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.

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BibTeXRIS

Sadowski, Greg. 2018-02-20. Low power adaptive synchronizer. https://www.osti.gov/biblio/1422725

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