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DOE OSTI · 1489513

Multiple core computer processor with globally-accessible local memories

Shalf, John·Donofrio, David·Oliker, Leonid
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Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

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97 MATHEMATICS AND COMPUTING

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Shalf, John, Donofrio, David, Oliker, Leonid. 2018-10-16. Multiple core computer processor with globally-accessible local memories. https://www.osti.gov/biblio/1489513

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