Quantum dot based memory devices: Current status and future prospect by simulation perspective

Abstract

We discuss the simulation of floating gate MOSFET memory performance consists of Si/Ge/Si quantum dots for electronics storage nodes with higk-κ material as the tunnel oxide. Heterostructure quantum dot was proposed to maintain the good memory performance without losing the long retention characteristic. As the results, retention time could be increase significantly without deteriorating the writing/erasing speed. By selected the dot size of 9–15nm and the tunnel oxide thickness of 2nm, the retention characteristic can reach up to 10{sup 9}s while the writing and erasing time at the order of 10{sup −6}s. By replace the SiO{sub 2} tunnel oxide with high-κ material such as HfO{sub 2}, ZrO{sub 2}, and Y{sub 2}O{sub 3} the leakage current due to the shrinkage of tunnel oxide thickness can be suppressed by the factor of 10 for the EOT lower than ∼1nm. Moreover, the charge-trapping that generated by the defect at Si substrate and higk-κ material interface are fully considered. We found that, the charge-trapping affects the retention time and memory operation performance. By increasing the charge-trapping depth and width, the memory operation time decrease significantly while the retention characteristic slightly improved.