DOE OSTI · 2506860
Preparing MPICH for exascale
Abstract
The advent of exascale supercomputers heralds a new era of scientific discovery, yet it introduces significant architectural challenges that must be overcome for MPI applications to fully exploit its potential. Among these challenges is the adoption of heterogeneous architectures, particularly the integration of GPUs to accelerate computation. Additionally, the complexity of multithreaded programming models has also become a critical factor in achieving performance at scale. The efficient utilization of hardware acceleration for communication, provided by modern NICs, is also essential for achieving low latency and high throughput communication in such complex systems. In response to these challenges, the MPICH library, a high-performance and widely used Message Passing Interface (MPI) implementation, has undergone significant enhancements. Here, this paper presents four major contributions that prepare MPICH for the exascale transition. First, we describe a lightweight communication stack that leverages the advanced features of modern NICs to maximize hardware acceleration. Second, our work showcases a highly scalable multithreaded communication model that addresses the complexities of concurrent environments. Third, we introduce GPU-aware communication capabilities that optimize data movement in GPU-integrated systems. Finally, we present a new datatype engine aimed at accelerating the use of MPI derived datatypes on GPUs. These improvements in the MPICH library not only address the immediate needs of exascale computing architectures but also set a foundation for exploiting future innovations in high-performance computing. By embracing these new designs and approaches, MPICH-derived libraries from HPE Cray and Intel were able to achieve real exascale performance on OLCF Frontier and ALCF Aurora respectively.
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Guo, Yanfei [Argonne National Laboratory (ANL), Argonne, IL (United States)] (ORCID:0000000237315423), Raffenetti, Ken [Argonne National Laboratory (ANL), Argonne, IL (United States)] (ORCID:0009000347052713), Zhou, Hui [Argonne National Laboratory (ANL), Argonne, IL (United States)] (ORCID:0000000244222911), Balaji, Pavan [Argonne National Laboratory (ANL), Argonne, IL (United States); Meta, Palo Alto, CA (United States)], Si, Min [Argonne National Laboratory (ANL), Argonne, IL (United States); Meta, Palo Alto, CA (United States)], Amer, Abdelhalim [Argonne National Laboratory (ANL), Argonne, IL (United States); Cerebras Systems, Sunnyvale, CA (United States)], Iwasaki, Shintaro [Argonne National Laboratory (ANL), Argonne, IL (United States); Meta, Palo Alto, CA (United States)], Seo, Sangmin [Argonne National Laboratory (ANL), Argonne, IL (United States); Klaytn Foundation (Singapore)], Congiu, Giuseppe [Argonne National Laboratory (ANL), Argonne, IL (United States); NVIDIA Corporation, Santa Clara, CA (United States)] (ORCID:0009000871657591), Latham, Robert [Argonne National Laboratory (ANL), Argonne, IL (United States)] (ORCID:0000000252856375), Oden, Lena [Argonne National Laboratory (ANL), Argonne, IL (United States); FernUniversität in Hagen (Germany)], Gillis, Thomas [Argonne National Laboratory (ANL), Argonne, IL (United States); NVIDIA Corporation, Santa Clara, CA (United States)] (ORCID:0000000197404746), Zambre, Rohit [NVIDIA Corporation, Santa Clara, CA (United States); Univ. of California, Irvine, CA (United States)], Ouyang, Kaiming [NVIDIA Corporation, Santa Clara, CA (United States); Univ. of California, Riverside, CA (United States)], Archer, Charles [Intel Corporation, Santa Clara, CA (United States)], Bland, Wesley [Meta, Palo Alto, CA (United States); Intel Corporation, Santa Clara, CA (United States)], Jose, Jithin [Intel Corporation, Santa Clara, CA (United States); Microsoft Corporation, Redmond, WA (United States)], Sur, Sayantan [NVIDIA Corporation, Santa Clara, CA (United States); Intel Corporation, Santa Clara, CA (United States)], Fujita, Hajime [Intel Corporation, Santa Clara, CA (United States); Fastly, San Francisco, CA (United States)], Durnov, Dmitry [Intel Corporation, Santa Clara, CA (United States)], Chuvelev, Michael [Intel Corporation, Santa Clara, CA (United States)], Zheng, Gengbin [Intel Corporation, Santa Clara, CA (United States)], Brooks, Alex [Intel Corporation, Santa Clara, CA (United States)], Thapaliya, Sagar [Intel Corporation, Santa Clara, CA (United States)], Doodi, Taru [NVIDIA Corporation, Santa Clara, CA (United States); Intel Corporation, Santa Clara, CA (United States)], Garazan, Maria [Intel Corporation, Santa Clara, CA (United States)], Oyanagi, Steve [Hewlett Packard Enterprise, Palo Alto, CA (United States)], Snir, Marc [Univ. of Illinois at Urbana-Champaign, IL (United States)], Thakur, Rajeev [Argonne National Laboratory (ANL), Argonne, IL (United States)] (ORCID:0000000255323048). 2025-01-09. Preparing MPICH for exascale. https://doi.org/10.1177/10943420241311608
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