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DOE OSTI · 2516809

Deploying Simulations to FPGAs for HIL-Style Tester Development

Wilke, Rudeger H. T. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)]
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Abstract

Hardware-in-the-Loop (HIL) methodologies for test system development often require simulations capable of running at MHz speeds on FPGAs. The stringent memory and speed constraints necessitate compromises between model fidelity and execution speed. Numerically solving the underlying governing equations represents the highest accuracy, but slowest responding approach. By storing pre-determined results in look-up-tables (LUT), one can balance speed and accuracy.

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Wilke, Rudeger H. T. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)]. 2025-01-01. Deploying Simulations to FPGAs for HIL-Style Tester Development. https://doi.org/10.2172/2516809

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