A Six-Phase Space Vector PWM Technique for Wide Bandgap Device-Based Three-Level Inverters

Abstract

This article presents a space vector pulsewidth modulation (SVPWM) technique for wide bandgap (WBG) device-based three-level (3L) six-phase inverters. Implementation of the SVPWM techniques for any six-phase inverter is complex for its high number of possible voltage vectors. Different six-phase load configurations are also possible depending on the angle between two consecutive phases and neutral point connections. The implementation techniques change depending on the load configuration. Moreover, a common neutral point for all six phases leads to circulating currents. Capacitor voltage balancing is also needed for 3L inverters. Capacitor voltage balancing and addressing the circulating current problem further increases the implementation complexity. In this article, a generalized SVPWM technique is proposed for the six-phase 3L inverters that is implementable using two three-phase 3L SVPWM blocks. The SVPWM technique also ensures dc bus capacitor voltage balancing and minimizes circulating current. Here, the SVPWM technique is experimentally verified using a GaN-based 3L six-phase active neutral point clamped (ANPC) inverter prototype, and the results are presented in this article.