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DOE OSTI · 3013377

A scalable superconducting nanowire memory array with row–column addressing

Abstract

Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers. Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. Here we report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm −2 . Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor. The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins. We achieve a minimum bit error rate of 10 −5 . Here, we also use circuit-level simulations to understand the memory cell’s dynamics, performance limits and stability under varying pulse amplitudes.

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BibTeXRIS

Medeiros, Owen [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0000000281448741), Castellani, Matteo [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0000000223697256), Karam, Valentin [Massachusetts Institute of Technology, Cambridge, MA (United States)], Foster, Reed [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0000000231002127), Simon, Alejandro [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0009000289698419), Incalza, Francesca [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0009000823459160), Butters, Brenden [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0000000266227633), Colangelo, Marco [Massachusetts Institute of Technology, Cambridge, MA (United States); Northeastern University, Boston, MA (United States)] (ORCID:0000000176110351), Berggren, Karl K. [Massachusetts Institute of Technology, Cambridge, MA (United States)] (ORCID:0000000174539031). 2026-01-06. A scalable superconducting nanowire memory array with row–column addressing. https://doi.org/10.1038/s41928-025-01512-0

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