DOE OSTI · 3395517
FOSS CAD for the Compact Verilog-A Model Standardization in Open Access PDKs
Abstract
This is a conference paper about open source tools for circuit simulation and model compilers.
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Grabinski, Wladek, Verley, Jason Christopher, Keiter, Eric Richard, Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal, Torri, Guilherme, Kusnetsov, Vadim, Tomaszewski, Daniel, Mueller, Markus, Kuthe, Pascal, Krattenmacher, Mario. 2024-03-01. FOSS CAD for the Compact Verilog-A Model Standardization in Open Access PDKs. https://doi.org/10.1109/edtm58488.2024.10511990
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