ghostbus v0.1.0

Abstract

Ghostbus is a Verilog meta-scripting tool which automates memory map creation, address assignment, and bus routing much like Register Description Language (RDL) and SystemRDL, but with a few stark differences. First, the design is entirely defined/captured within the Verilog/SystemVerilog codebase (no extra second language). Second, the Verilog code remains valid even without the auto-generated code, enhancing modularity and compatibility with other tools/workflows.