Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0

Abstract

Hardware simulation is an indispensable tool for designing chips as well as researching future architectures. Unfortunately, the slow rate of simulation can often bottleneck the design process, as designers must wait to see the results of a simulation before changing the design and starting a new simulation. The Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) is a tool designed to accelerate hardware simulations. ESSENT takes in a design, uses graph algorithms to identify opportunities for conditional execution, and generates a simulator that leverages these opportunities. The generated simulator produces the exact same simulation results that would be returned by an unoptimized simulator, but in substantially less time. For input, ESSENT takes in designs formatted in FIRRTL (an open format).