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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Experimental Performance of a Micromachined Heat Flux Sensor

Steady-state and frequency response calibration of a microfabricated heat-flux sensor have been completed. This sensor is batch fabricated using standard, micromachining techniques, allowing both miniaturization and the ability to create arrays of sensors and their corresponding interconnects. Both high-frequency and spatial response is desired, so the sensors are both thin and of small cross-sectional area. Thin-film, temperature-sensitive resistors are used as the active gauge elements. Two sensor configurations are investigated: (1) a Wheatstone-bridge using four resistors; and (2) a simple, two-resistor design. In each design, one resistor (or pair) is covered by a thin layer (5000 A) thermal barrier; the other resistor (or pair) is covered by a thick (5 microns) thermal barrier. The active area of a single resistor is 360 microns by 360 microns; the total gauge area is 1.5 mm square. The resistors are made of 2000 A-thick metal; and the entire gauge is fabricated on a 25 microns-thick flexible, polyimide substrate. Heat flux through the surface changes the temperature of the resistors and produces a corresponding change in resistance. Sensors were calibrated using two radiation heat sources: (1) a furnace for steady-state, and (2) a light and chopper for frequency response.

TEMPERATURE SENSITIVE ELEMENTS↗
NASA NTRS2008

Ring Bus Architecture for a Solid-State Recorder

A document concisely describes a ring bus architecture for a proposed solid-state recorder (SSR) that would serve as buffer of data to be transmitted from a spacecraft to Earth. This architecture would afford fault tolerance needed for reliable operation in an anticipated high-radiation environment in which traditional SSRs cannot operate reliably. Features of the architecture include one or more controller boards and multiple memory boards interconnected in a ringlike topology. The interconnections would be high-speed serial links complying with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus). Accordingly, each controller and memory board would be equipped with an IEEE-1393-compliant ring-bus-interface unit. The ringlike topology and the multiplicity of memory boards (and, optionally, of controller boards) would afford the redundancy needed for fault tolerance. Each board would be a fault-containment region. The IEEE 1393 links could be routed so that the SSR would continue to function even in the event of multiple failures. This architecture would also support scalability over a wide range. In a fully redundant configuration, it could accommodate between 1 and 125 memory boards.

Walker, W. John↗
NASA NTRS2015

Thin, Flexible IMM Solar Array

NASA needs solar arrays that are thin, flexible, and highly efficient; package compactly for launch; and deploy into large, structurally stable high-power generators. Inverted metamorphic multijunction (IMM) solar cells can enable these arrays, but integration of this thin crystalline cell technology presents certain challenges. The Thin Hybrid Interconnected Solar Array (THINS) technology allows robust and reliable integration of IMM cells into a flexible blanket comprising standardized modules engineered for easy production. The modules support the IMM cell by using multifunctional materials for structural stability, shielding, coefficient of thermal expansion (CTE) stress relief, and integrated thermal and electrical functions. The design approach includes total encapsulation, which benefits high voltage as well as electrostatic performance.

Walmsley, Nicholas↗
NASA NTRS1993

Portable computer system architecture for the Space Station Freedom program

This paper outlines various mission requirements and technical approaches that support the potential use of portable computers in several defined activities within the Space Station Freedom (SSF) program. Specifically, the use of portable computers as consoles for both spacecraft control and payload applications is presented. Various issues and proposed solutions regarding the incorporation of portable computers within the program are presented. The primary issues presented regard architecture (standard interface for expansion, advanced processors and displays), integration (methods of high-speed data communication, peripheral interfaces, and interconnectivity within various support networks), and evolution (wireless communications and multimedia data interface methods).

Alena, Richard↗
NASA NTRS2020

NASA SpaceCube Intelligent Multi-Purpose System for Enabling Remote Sensing, Communication, and Navigation in Mission Architectures

New, innovative CubeSat mission concepts demand modern capabilities such as artificial intelligence and autonomy, constellation coordination, fault mitigation, and robotic servicing –all of which require vastly more processing resources than legacy systems are capable of providing. Enabling these domains within a scalable, configurable processing architecture is advantageous because it also allows for the flexibility to address varying mission roles, such as a command and data-handling system, a high-performance application processor extension, a guidance and navigation solution, or an instrument/sensor interface. This paper describes the NASA SpaceCube Intelligent Multi-Purpose System (IMPS), which allows mission developers to mix-and-match 1U (10 cm × 10 cm) CubeSat payloads configured for mission-specific needs. The central enabling component of the system architecture to address these concerns is the SpaceCube v3.0 Mini Processor. This single-board computer features the 20nm Xilinx Kintex UltraScale FPGA combined with a radiation-hardened FPGA monitor, and extensive IO to integrate and interconnect varying cards within the system. To unify the re-usable designs within this architecture, the CubeSat Card Standard was developed to guide design of 1U cards. This standard define spinout configurations, mechanical, and electrical specifications for 1U CubeSat cards, allowing the backplane and mechanical enclosure to be easily extended. NASA has developed several cards adhering to the standard (System-on-Chip, power card, etc.), which allows the flexibility to configure a payload from a common catalog of cards.

Advanced Avionics, Hybrid Processing, Data Process↗
NASA NTRSDate not supplied

A Photon Counting Ground Receiver for Free-Space Optical Communications

The National Aeronautics and Space Administration is developing a photon counting ground receiver for free-space optical communications. The receiver consists of a fiber interconnect, superconducting nanowire single photon counting detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. This receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency standard, which is used in the low photon flux communications regime, including on the upcoming Optical Artemis-2 Orion communications demonstration. The receiver architecture is modular, can be scaled for data rate, and is designed with primarily commercial-off-the-shelf technology. Two fiber interconnect and detector architectures are being prototyped. The first uses a few-mode-fiber coupled to a 16-channel SNSPD array and the second architecture uses a photonic lantern coupled to 7 single-pixel SNSPDs. Photon counting, symbol timing recovery, demodulation and decoding is done using several FPGA cards. This presentation describes the unique features of the ground receiver, performance test results, and challenges with using commercial SNSPDs in free-space optical communications.

Jennifer N Downey↗
DOE OSTI2020

Nanometal-Interconnected Carbon Conductors (NICCS) for Advanced Electric Machines (RIT Final Technical Report)

Recent advancements in carbon nanotube (CNT) research have enabled lightweight, conductive wires as a transformative technology. Metal-carbon nanotube (CNT) hybrid conductors aim to combine the high conductivity of traditional metals with the low mass and temperature coefficient of resistance (TCR) of carbon nanotubes. The high conductivity of copper makes it a promising candidate to combine with CNTs in a hybrid structure, but there is limited physical and electrical interaction between copper and CNTs. The use of an interfacial layer offers one method of improving the interconnection of a Cu-CNT hybrid conductor. Over the course of this grant, a joule heating-driven chemical vapor deposition (CVD) technique was developed to deposit nanometal seeds throughout a porous, low-density (0.12 g/cm 3 , ~10 tex or mg/m) CNT roving template. Modification of the applied current to the CNT roving allows for the tuning of depositions towards either hot-spot site-specificity or overall uniformity. The effects of temperature, pressure, precursor mass, and the interval of applied current were investigated, demonstrating nanometal depositions ranging from less than 5 % w/w to over 85 % w/w. The versatility of CVD allows for a wide variety of metals to be deposited including copper, titanium, nickel, silver, tungsten, palladium, platinum, ruthenium, rhodium, and iridium. One preferred demonstration involved using platinum depositions to improve the electrical properties of metal-seeded CNTs across all mass loadings studied. Moreover, when the metal-seeded CNT wires were electroplated with copper, densified, and annealed under hydrogen/argon; the result was a Cu-CNT hybrid conductor with the highest conductivities reported to date. The good interconnection of the metal and CNT portions results in a stable conductor. An electrical conductivity of 16-20 MS/m was achieved for multiple Cu-CNT hybrid conductors at 150 °C, which exceeds the program goal for conductivity of greater than 15 MS/m for a 1 m long CNT wire. Overall, the research outcomes from the project showed improvements in CNT wire fabrication from roll-to-roll CVD grown carbon nanotube wires using nanometal interconnects to bridge CNT-to-CNT junctions, thus mitigating network contact resistances. Advanced nanometal interconnected carbon conductors (NICCs) were developed as a means to achieve novel light-weight wiring appropriate for applications that require the conductivity of metallic (i.e., Cu, Al, etc.) wires at elevated temperatures. High conductivity, low TCR electrical conductors such as the nanometal interconnected Cu-CNT hybrids have numerous future applications towards high efficiency motors, generators, and transformers. Specifically, the advanced wires have the ability to operate at lower resistance during conditions for standard electric motors at 150 °C, which would improve the electrical efficiency while lowering energy needs.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Regulatory and Technical Challenges and Barriers to Adoption of Distributed Wind Energy in Agricultural Settings

Distributed wind (DW) energy development can benefit agricultural landowners through the possibility of improved resilience of electrical service from onsite generation and associated economic benefits. DW development currently faces technical and regulatory challenges related to interconnection of projects with distribution or transmission equipment on the main electrical grid. A review was conducted of barriers to adoption for agricultural DW projects and potential roles of various stakeholders in addressing them. One major barrier is that the unique characteristics of wind energy generation such as its variability and intermittency, may require upgrades for the whole power line, which can lead to prohibitive cost burdens on individual interconnection customers. Another barrier is compliance with federal, state, or utility-level regulations that require technology-agnostic, industry-standard equipment that is often not technically realistic for DW projects. DW developers, grid infrastructure owner-operators, regulators, and standards publishers can work together to address these challenges and facilitate DW development.

17 WIND ENERGY↗
NASA NTRS1981

CADAT place-and-routine in two dimensions

CADAT place-and-route-in-two dimensions program (PR2D) is standard-cell automatic-layout program for generating large-scale-integrated/metal-oxidesemiconductor (LSI/MOS) arrays. PR2D translates logic designer's cell interconnection requirements into physically-defined MOS chip. PR2D reads input data, searches pin data file for data on each pattern type, generates placement of patterns, and interconnects patterns. As output, it generates artwork for layouts.

Source record↗
NASA NTRS1991

Neural Networks Of VLSI Components

Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.

Eberhardt, Silvio P.↗
NASA NTRS1978

SIFT - Design and analysis of a fault-tolerant computer for aircraft control

SIFT (Software Implemented Fault Tolerance) is an ultrareliable computer for critical aircraft control applications that achieves fault tolerance by the replication of tasks among processing units. The main processing units are off-the-shelf minicomputers, with standard microcomputers serving as the interface to the I/O system. Fault isolation is achieved by using a specially designed redundant bus system to interconnect the processing units. Error detection and analysis and system reconfiguration are performed by software. Iterative tasks are redundantly executed, and the results of each iteration are voted upon before being used. Thus, any single failure in a processing unit or bus can be tolerated with triplication of tasks, and subsequent failures can be tolerated after reconfiguration. Independent execution by separate processors means that the processors need only be loosely synchronized, and a novel fault-tolerant synchronization method is described.

Wensley, J. H.↗
NASA NTRS1981

Limited evaluation of an F-14A airplane utilizing an aileron-rudder interconnect control system in the landing configuration

A flight test was conducted for preliminary evaluation of an aileron-rudder interconnect (ARI) control system for the F-14A airplane in the landing configuration. Two ARI configurations were tested in addition to the standard F-14 flight control system. Results of the flight test showed marked improvement in handling qualities when the ARI systems were used. Sideslip due to adverse yaw was considerably reduced, and airplane turn rate was more responsive to pilot lateral control inputs. Pilot comments substantiated the flight data and indicated that the ARI systems were superior to the standard control system in terms of pilot capability to make lateral offset corrections and heading changes on final approach.

Kelley, W. W.↗
NASA NTRS2011

Radiation-Tolerant, SpaceWire-Compatible Switching Fabric

Current and future near-Earth and deep space exploration programs and space defense programs require the development of robust intra-spacecraft serial data transfer electronics that must be reconfigurable, fault-tolerant, and have the ability to operate effectively for long periods of time in harsh environmental conditions. Existing data transfer systems based on state-of-the-art serial data transfer protocols or passive backplanes are slow, power-hungry, and poorly reconfigurable. They provide limited expandability and poor tolerance to radiation effects and total ionizing dose (TID) in particular, which presents harmful threats to modern submicron electronics. This novel approach is based on a standard library of differential cells tolerant to TID, and patented, multi-level serial interface architecture that ensures the reliable operation of serial interconnects without application of a data-strobe or other encoding techniques. This proprietary, high-speed differential interface presents a lowpower solution fully compatible with the SpaceWire (SW) protocol. It replaces a dual data-strobe link with two identical independent data channels, thus improving the system s tolerance to harsh environments through additional double redundancy. Each channel incorporates an automatic line integrity control circuitry that delivers error signals in case of broken or shorted lines.

Katzman, Vladimir↗
DOE OSTI2024

Assessment and Coordination of EVSE Cybersecurity Standards

Cybersecurity certification programs for Electric Vehicle Supply Equipment (EVSE) are fragmented due to no single certification covering all aspects of the device and additionally the existence of multiple programs and under different levels of regulation. These devices are also confronted by the intricate assembly of product software, firmware, and hardware. Devices contain both logical and physical interfaces. These multifaceted devices have vulnerabilities at many levels and interconnect with other potentially vulnerable systems including the electric vehicle, the cloud where data and payment information are stored, and the electric grid and electric grid equipment including utilities. Of the EVSE certification programs that are found, none are directly for the cybersecurity of EVSE. Many standards are for safety, specifically battery safety, some are cybersecurity standards for other types of equipment and can be modeled for EVSE. In specific, ISA/IEC 62443 is found to be significantly in line with EVSE security needs and will be used in future testing to certify EVSE and help guide the project to demonstrate where gaps exist, where strengths lie in the standard and how this can be used to lead the certification efforts in harmonizing EVSE cybersecurity standards. In addition, there are multiple efforts that are currently seeking to build EVSE standards or revise existing standards to address gaps. This effort is seeking to establish a cybersecurity program for EVSE that will inform customers and help increase the level of security across products and state EVSE procurements to achieve consistency across different jurisdictions.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2023

Productivity frameworks for HPC

Productivity Frameworks for HPC will include container recipes, build recipes, continuous integration scripts, and other software aimed at testing the portability of containerized HPC software across platforms and interconnects. In particular, it tests the utility of bind-mounting at the MPI layer (rather than the underlying fabric layer) to leverage a standardized protocol and avoid various technical debt and vendor lock-in. Since MPIs are often ABI-incompatible, trampolines such as the open-source Wi4MPI will be tested when such cases arise.

Hanford, Nathan↗
DOE OSTI2022

Distributed Energy Resource Cybersecurity Standards Development [Final Report]

Currently, the solar industry is operating with little application-specific guidance on how to protect and defend their systems from cyberattacks. This 3-year Department of Energy (DOE) Solar Energy Technologies Office-funded project helped advance the distributed energy resource (DER) cybersecurity state-of-the-art by (a) bolstering industry awareness of cybersecurity concepts, risks, and solutions through a webinar series and (b) developing recommendations for DER cybersecurity standards to improve the security performance of DER products and networks. Drafting DER standards is a lengthy, consensus-based process requiring effective leadership and stakeholder participation. This project was designed to reduce standard and guide writing times by creating well-researched recommendations that could act as a starting place for national and international standards development organizations. Working within the SunSpec/Sandia DER Cybersecurity Workgroup, the team produced guidance for DER cybersecurity certification, communication protocol standards, network architecture s, access control, and patching. The team also led subgroups within the IEEE P 1547.3 Guide for Cybersecurity of Distributed Energy Resources Interconnected with Electric Power Systems committee and pushed a draft to ballot in October 2021.

14 SOLAR ENERGY↗
NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗