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177 records · Page 10

Prioritization methodology for chemical replacement

Since United States of America federal legislation has required ozone depleting chemicals (class 1 & 2) to be banned from production, The National Aeronautics and Space Administration (NASA) and industry have been required to find other chemicals and methods to replace these target chemicals. This project was initiated as a development of a prioritization methodology suitable for assessing and ranking existing processes for replacement 'urgency.' The methodology was produced in the form of a workbook (NASA Technical Paper 3421). The final workbook contains two tools, one for evaluation and one for prioritization. The two tools are interconnected in that they were developed from one central theme - chemical replacement due to imposed laws and regulations. This workbook provides matrices, detailed explanations of how to use them, and a detailed methodology for prioritization of replacement technology. The main objective is to provide a GUIDELINE to help direct the research for replacement technology. The approach for prioritization called for a system which would result in a numerical rating for the chemicals and processes being assessed. A Quality Function Deployment (QFD) technique was used in order to determine numerical values which would correspond to the concerns raised and their respective importance to the process. This workbook defines the approach and the application of the QFD matrix. This technique: (1) provides a standard database for technology that can be easily reviewed, and (2) provides a standard format for information when requesting resources for further research for chemical replacement technology. Originally, this workbook was to be used for Class 1 and Class 2 chemicals, but it was specifically designed to be flexible enough to be used for any chemical used in a process (if the chemical and/or process needs to be replaced). The methodology consists of comparison matrices (and the smaller comparison components) which allow replacement technology to be quantitatively compared in several categories, and a QFD matrix which allows process/chemical pairs to be rated against one another for importance (using consistent categories). Depending on the need for application, one can choose the part(s) needed or have the methodology completed in its entirety. For example, if a program needs to show the risk of changing a process/chemical one may choose to use part of Matrix A and Matrix C. If a chemical is being used, and the process must be changed; one might use the Process Concerns part of Matrix D for the existing process and all possible replacement processes. If an overall analysis of a program is needed, one may request the QFD to be completed.

Cruit, Wendy↗

AMD Radeon e9173 Low Power PCIE GPU Single Event Effects Test Report

The AMD Radeon Embedded e9170 Graphics Processing Unit (GPU), notably the e9173 Peripheral Component Interconnect Express (PCIE) variant, is of interest to Artemis generation programs with requirements for graphics rendering, compute, artificial intelligence (Ai) with a constraints-requiring piece-part procurement and power consumption of less than 50W. In addition to collecting heavy ion data on this device, a secondary purpose of this test campaign was to validate video capture hardware and software workflows used with GPU, microprocessor and system-on-chip device testing. Five (5) test patterns from the NEPP Processor Enclave (NPE) test suite were used with the e9173. The test patterns covered the operating system’s (OS) idle contribution towards the cross section, matrix math using tensorflow-rocm, two artificial intelligence models developed at NASA GSFC, and an industry standard GPU benchmarking application called Mesa GLXGears.

NASA Technical Memorandum (TM) test report for pos↗

Performance Monitoring of Distributed Data Processing Systems

Test and checkout systems are essential components in ensuring safety and reliability of aircraft and related systems for space missions. A variety of systems, developed over several years, are in use at the NASA/KSC. Many of these systems are configured as distributed data processing systems with the functionality spread over several multiprocessor nodes interconnected through networks. To be cost-effective, a system should take the least amount of resource and perform a given testing task in the least amount of time. There are two aspects of performance evaluation: monitoring and benchmarking. While monitoring is valuable to system administrators in operating and maintaining, benchmarking is important in designing and upgrading computer-based systems. These two aspects of performance evaluation are the foci of this project. This paper first discusses various issues related to software, hardware, and hybrid performance monitoring as applicable to distributed systems, and specifically to the TCMS (Test Control and Monitoring System). Next, a comparison of several probing instructions are made to show that the hybrid monitoring technique developed by the NIST (National Institutes for Standards and Technology) is the least intrusive and takes only one-fourth of the time taken by software monitoring probes. In the rest of the paper, issues related to benchmarking a distributed system have been discussed and finally a prescription for developing a micro-benchmark for the TCMS has been provided.

Ojha, Anand K.↗

Suggestions for Layout and Functional Behavior of Software-Based Voice Switch Keysets

Marshall Space Flight Center (MSFC) provides communication services for a number of real time environments, including Space Shuttle Propulsion support and International Space Station (ISS) payload operations. In such settings, control team members speak with each other via multiple voice circuits or loops. Each loop has a particular purpose and constituency, and users are assigned listen and/or talk capabilities for a given loop based on their role in fulfilling the purpose. A voice switch is a given facility's hardware and software that supports such communication, and may be interconnected with other facilities switches to create a large network that, from an end user perspective, acts like a single system. Since users typically monitor and/or respond to several voice loops concurrently for hours on end and real time operations can be very dynamic and intense, it s vital that a control panel or keyset for interfacing with the voice switch be a servant that reduces stress, not a master that adds it. Implementing the visual interface on a computer screen provides tremendous flexibility and configurability, but there s a very real risk of overcomplication. (Remember how office automation made life easier, which led to a deluge of documents that made life harder?) This paper a) discusses some basic human factors considerations related to keysets implemented as application software windows, b) suggests what to standardize at the facility level and what to leave to the user's preference, and c) provides screen shot mockups for a robust but reasonably simple user experience. Concepts apply to keyset needs in almost any type of operations control or support center.

Scott, David W.↗

NASA Tech Briefs, November 2009

Topics covered include: Cryogenic Chamber for Servo-Hydraulic Materials Testing; Apparatus Measures Thermal Conductance Through a Thin Sample from Cryogenic to Room Temperature; Rover Attitude and Pointing System Simulation Testbed; Desktop Application Program to Simulate Cargo-Air-Drop Tests; Multimodal Friction Ignition Tester; Small-Bolt Torque-Tension Tester; Integrated Spacesuit Audio System Enhances Speech Quality and Reduces Noise; Hardware Implementation of a Bilateral Subtraction Filter; Simple Optoelectronic Feedback in Microwave Oscillators; Small X-Band Oscillator Antennas; Free-Space Optical Interconnect Employing VCSEL Diodes; Discrete Fourier Transform Analysis in a Complex Vector Space; Miniature Scroll Pumps Fabricated by LIGA; Self-Assembling, Flexible, Pre-Ceramic Composite Preforms; Flight-speed Integral Image Analysis Toolkit; Work Coordination Engine; Multi-Mission Automated Task Invocation Subsystem; Autonomously Calibrating a Quadrupole Mass Spectrometer; Determining Spacecraft Reaction Wheel Friction Parameters; Composite Silica Aerogels Opacified with Titania; Multiplexed Colorimetric Solid-Phase Extraction; Detecting Airborne Mercury by Use of Polymer/Carbon Films; Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate; Pressure-Energized Seal Rings to Better Withstand Flows; Rollerjaw Rock Crusher; Microwave Sterilization and Depyrogenation System; Quantifying Therapeutic and Diagnostic Efficacy in 2D Microvascular Images; NiF2/NaF:CaF2/Ca Solid-State High-Temperature Battery Cells; Critical Coupling Between Optical Fibers and WGM Resonators; Microwave Temperature Profiler Mounted in a Standard Airborne Research Canister; Alternative Determination of Density of the Titan Atmosphere; Solar Rejection Filter for Large Telescopes; Automated CFD for Generation of Airfoil Performance Tables; Progressive Classification Using Support Vector Machines; Active Learning with Irrelevant Examples; A Data Matrix Method for Improving the Quantification of Element Percentages of SEM/EDX Analysis; Deployable Shroud for the International X-Ray Observatory; Improved Model of a Mercury Ring Damper; Optoelectronic pH Meter: Further Details; X-38 Advanced Sublimator; and Solar Simulator Represents the Mars Surface Solar Environment.

Source record↗

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗

Characterization of MMIC devices for active array antennas

Certain aspects of monolithic microwave integrated circuit (MMIC) interconnectivity were investigated. Considerations that lead to preserving the inherently reproducible characteristics of the MMIC are proposed. It is shown that at radio frequencies (RF) greater than 20 GHz, the transition from the MMIC device to other transmission media must be an accurate RF match. It is proposed that the RF match is sufficiently critical to include the transition as part of the delivered MMIC package. The model to analyze several transitions is presented. This model consists of a succession of abrupt discontinuities in printed circuit transmission lines. The analysis of these discontinuities is achieved by the Spectral Galerkin technique, to establish the modes and mode matching, to generate the generalized S parameters of the individual discontinuities. Preliminary results achieved with this method are presented. It is concluded that special effects should be coordinated by the active array antenna industry toward standardization of MMIC packaging and characterization.

Smetana, J.↗

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗

Numerical Modeling of the Chilldown of Cryogenic Transfer Lines Using a Sinda/GFSSP Integrated Solver

An important first step in cryogenic propellant loading is the chilldown of transfer lines. During the chilldown of the transfer line, the flow is two-phase and unsteady, with solid to fluid heat transfer and therefore a coupled thermo-fluid analysis is necessary to model the system. This paper describes a numerical model of pipe chilldown that utilizes the Sinda/GFSSP Conjugate Integrator (SGCI). SGCI is a new analysis tool developed at NASA's Marshall Space Flight Center (MSFC). SGCI facilitates the solution of thermofluid problems in interconnected solid-fluid systems. The solid component of the system is modeled in MSC Patran and translated into an MSC Sinda thermal network model. The fluid component is modeled in GFSSP, the Generalized Fluid System Simulation Program. GFSSP is a general network flow solver developed at NASA/MSFC. GFSSP uses a finite-volume approach to model fluid systems that can include phase change, multiple species, fluid transients, and heat transfer to simple solid networks. SGCI combines the GFSSP Fortran code with the Sinda input file and compiles the integrated model. Sinda solves for the temperatures of the solid network, while GFSSP simultaneously solves the fluid network for pressure, temperature, and flow rate. The two networks are coupled by convection heat transfer from the solid wall to the cryogenic fluid. The model presented here is based on a series of experiments conducted in 1966 by the National Bureau of Standards (NBS). A vacuum-jacketed, 200 ft copper transfer line was chilled by liquid nitrogen and liquid hydrogen. The predictions of transient temperature profiles and chilldown time of the integrated Sinda/GFSSP model will be compared to the experimental measurements.

LeClair, Andre↗

Quartz/fused silica chip carriers

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Source record↗

High-performance mass storage system for workstations

Reduced Instruction Set Computer (RISC) workstations and Personnel Computers (PC) are very popular tools for office automation, command and control, scientific analysis, database management, and many other applications. However, when using Input/Output (I/O) intensive applications, the RISC workstations and PC's are often overburdened with the tasks of collecting, staging, storing, and distributing data. Also, by using standard high-performance peripherals and storage devices, the I/O function can still be a common bottleneck process. Therefore, the high-performance mass storage system, developed by Loral AeroSys' Independent Research and Development (IR&D) engineers, can offload a RISC workstation of I/O related functions and provide high-performance I/O functions and external interfaces. The high-performance mass storage system has the capabilities to ingest high-speed real-time data, perform signal or image processing, and stage, archive, and distribute the data. This mass storage system uses a hierarchical storage structure, thus reducing the total data storage cost, while maintaining high-I/O performance. The high-performance mass storage system is a network of low-cost parallel processors and storage devices. The nodes in the network have special I/O functions such as: SCSI controller, Ethernet controller, gateway controller, RS232 controller, IEEE488 controller, and digital/analog converter. The nodes are interconnected through high-speed direct memory access links to form a network. The topology of the network is easily reconfigurable to maximize system throughput for various applications. This high-performance mass storage system takes advantage of a 'busless' architecture for maximum expandability. The mass storage system consists of magnetic disks, a WORM optical disk jukebox, and an 8mm helical scan tape to form a hierarchical storage structure. Commonly used files are kept in the magnetic disk for fast retrieval. The optical disks are used as archive media, and the tapes are used as backup media. The storage system is managed by the IEEE mass storage reference model-based UniTree software package. UniTree software will keep track of all files in the system, will automatically migrate the lesser used files to archive media, and will stage the files when needed by the system. The user can access the files without knowledge of their physical location. The high-performance mass storage system developed by Loral AeroSys will significantly boost the system I/O performance and reduce the overall data storage cost. This storage system provides a highly flexible and cost-effective architecture for a variety of applications (e.g., realtime data acquisition with a signal and image processing requirement, long-term data archiving and distribution, and image analysis and enhancement).

Chiang, T.↗

MSFC institutional area network and ATM technology

The New Institutional Area Network (NEWIAN) at Marshall supports over 5000 end users with access to 26 file servers providing work presentation services. It is comprised of some 150 Ethernet LAN's interconnected by bridges/routers which are in turn connected to servers over two dual FDDI rings. The network supports various higher level protocols such as IP, IPX, AppleTalk (AT), and DECNet. At present IPX and AT protocols packets are routed, and IP protocol packets are bridged; however, work is in progress to route all IP packets. The impact of routing IP packets on network operation is examined. Broadband Integrated Services Data Network (BISDN), presently at various stages of development, is intended to provide voice, video, and data transfer services over a single network. BISDN will use asynchronous transfer mode (ATM) as a data transfer technique which provides for transmission, multiplexing, switching, and relaying of small size data units called cells. Limited ATM Wide Area Network (WAN) services are offered by Wiltel, AT&T, Sprint, and others. NASA is testing a pilot ATM WAN with a view to provide Program Support Communication Network services using ATM. ATM supports wide range of data rates and quality of service requirements. It is expected that ATM switches will penetrate campus networks as well. However, presently products in these areas are at various stages of development and standards are not yet complete. We examine development of ATM to help assess its role in the evolution of NEWIAN.

Amin, Ashok T.↗

NASA Earth Systems Digital Twins (ESDT)

"Similarly to artificial intelligence, which is now revolutionizing many aspects of our daily lives, Earth system digital twin technologies have the potential to revolutionize the way Earth Science research will be conducted in the future, and how results and knowledge from this research will provide information to support decision making and yield impactful societal benefits. An Earth System Digital Twin or ESDT is a dynamic and interactive information system that first provides a digital replica of the past and current states of the Earth or Earth system as accurately and timely as possible; second, allows for computing forecasts of future states under nominal assumptions and based on the current replica; and third, offers the capability to investigate many hypothetical scenarios under varying impact assumptions. In other words, an ESDT provides the integrated What-Now, What-Next, and What-If pictures of the Earth or Earth system, by continuously ingesting newly observed data and by leveraging multiple interconnected models, machine learning as well advanced computing and visualization capabilities. Digital twins have been developed in engineering since 2002, but the interest in digital twins for the Earth domain is more recent and stems from the convergence of several developments: - The huge amount of diverse data that has now been collected continuously for more than 50 years, and that is becoming more and more difficult to access, understand, and utilize. - At the same time, because of climate change and its impacts the information produced by all of this data is becoming of interest to many new non-traditional users for analyzing and predicting various phenomena. - Because of advances in computational and visualization capabilities and the parallel unprecedented development of machine learning (ML), extracting relevant information from these large amounts of data and running complex models faster has become possible. As a result, it is becoming necessary and possible to build intuitive and interactive frameworks that will enable users with various skill levels and/or organizational hierarchy levels to easily access large amounts of targeted information along with the relevant tools and models (Earth system and human activity models), to support them in analyzing and visualizing this information, to help them understand interactions among models, to visualize the potential outcomes of various impacts, and to support decision or policy making. The full power of digital twins is that, through an integrated representation and standardized tools and software technologies, the same digital replica can address the needs of multiple users at various resolutions (spatial and temporal) and for various applications (science, economic, policy, etc.) – “from farmer to scientist”. With all these interests at stake, the challenges of building optimal digital twins are many and complex. The first challenge is to determine if a Digital Twin should be global or local, and multi-domain or thematic. For example, some domains such as Climate or Weather will require a global Digital Twin or Digital Twin capabilities while science areas such as Biodiversity might be more local. We can also envision that multiple thematic ESDTs, e.g., Air Quality, Wildfires, Hydrology could be federated or provide input to other ESDTs, either on a regional level or to a more global ESDT. Overall, we can imagine a future “web” of Digital Twins co-existing in a hierarchy or in a network, and capable of being connected or federated depending on the needs. This last point brings up the very important challenge of interoperability, including standards and protocols that will need to be built into these systems from the beginning. Each individual digital twin would have full flexibility in internal construction but would need standards-based interfaces (input and output) or hooks to make it compatible with others. Another challenge when building digital twins will be to decide how to organize each digital replica. Based on the applications targeted by the DT under implementation, various amounts and types of raw data, Analysis Ready Data (ARD) and information will need to be incorporated. Depending on the required latencies and needs of the users, various solutions can be considered, including Data Cubes, Data Lakes, pointers, or computing information on demand. We envision that each ESDT will choose a solution adapted to its specific objectives. Another important challenge is the type(s) of visualization that will be used, as well as the level of interactivity and refresh rate that will be required. Again, this will depend on the objectives of the ESDT, but also on the various users’ needs. In most cases, several types of visualizations and human interfaces will need to be offered depending on the projected users of that system. In parallel to the challenges highlighted above, there are also many tools and technologies that will need to be developed or improved for all types of digital twins. Among those are improved machine learning technologies, for example providing explainability, but also ML techniques for causality and providing a better integration of physics models. Additionally, reliable uncertainty quantification methods will be needed for all ESDT components, from validating data fusion and assimilation to assessing the accuracy of ML models and weighing the values of decisions supported by those systems. This presentation introduces the ESDT concept, presents several ESDT use cases, and a proposed ESDT architecture framework, as well as various technologies being developed by the Advanced Information Systems Technology (AIST) Program."

Earth Science Remote Sensing; Information Systems↗

From Research to Reality -- Challenges and Opportunities in Complex System Design

The scope and scale of our interconnected society requires that we view the world through a complex system lens, where numerous parts interact, and emergent behaviors are the norm. Understanding complex systems is critical for decision-making and policy development in domains such as ecological systems, financial markets, supply chains, and global transportation systems, where decision-makers need reliable information to predict the impact of decisions that may play out over decades. Traditional approaches to the research that produces this information are often insufficient, where hypotheses are tested in an isolated environment, and where the results may not carry over to the integrated system. There are a multitude of advancements in system engineering, artificial intelligence, and test and evaluation that are emerging to meet the challenge. Approaches such as agile development, model-based system engineering, design of experiments, large language models, and formal ontologies are providing ways to manage complexity and increase our collective ability to make the changes that we want to see in the world. In this talk I will provide a few examples related to the architecture of the National Airspace System (NAS), where we have investigated the use of large language models, basic formal ontology, and applied category theory to help researchers and system engineers be more effective in this complex design space. Bio: Dr. Ian Levitt’s current research focus is on the complex evolution of the National Airspace System. Prior to joining NASA in 2020, he was with the FAA leading international standards and national laboratory development for the agency. Dr. Levitt earned his PhD in mathematics from Rutgers University in 2009. His mission is to promote a healthy and continuous transformation of society through open information and cooperation.

Ian Levitt↗

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Le, Binh Q.↗