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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10

Arbitrary electro-optic bandwidth and frequency control in lithium niobate optical resonators

In situ tunable photonic filters and memories are important for emerging quantum and classical optics technologies. However, most photonic devices have fixed resonances and bandwidths determined at the time of fabrication. Here we present an in situ tunable optical resonator on thin-film lithium niobate. By leveraging the linear electro-optic effect, we demonstrate widely tunable control over resonator frequency and bandwidth on two different devices. We observe up to ∼50 × tuning in the bandwidth over ∼50 V with linear frequency control of ∼230 MHz/V. We also develop a closed-form model predicting the tuning behavior of the device. This paves the way for rapid phase and amplitude control over light transmitted through our device.

42 ENGINEERING↗

Sampling video compression system

A system for transmitting video signal of compressed bandwidth is described. The transmitting station is provided with circuitry for dividing a picture to be transmitted into a plurality of blocks containing a checkerboard pattern of picture elements. Video signals along corresponding diagonal rows of picture elements in the respective blocks are regularly sampled. A transmitter responsive to the output of the sampling circuitry is included for transmitting the sampled video signals of one frame at a reduced bandwidth over a communication channel. The receiving station is provided with a frame memory for temporarily storing transmitted video signals of one frame at the original high bandwidth frequency.

Matsumoto, Y.↗

The development of lossless data compression technology for remote sensing applications

Lossless data compression has been studied for many NASA missions to achieve the benefit of increased science return, reduced onboard memory requirement, station contact time and communication bandwidth. This paper first addresses the requirement for onboard applications and provides rational for the selection of the Rice algorithm among other available techniques. A top-level description of the Rice algorithm will be given, along with some new capabilities already implemented in both software and hardware VLSI forms. The paper then addresses systems issues important for onboard implementation including sensor calibration, error propagation and data packetization. The latter part of the paper provides several case study examples drawn from a broad spectrum of science instruments including the thematic mapper, x-ray telescope, gamma-ray spectrometer, and acousto-optical spectrometer.

Yeh, Pen-Shu↗

Parallel Rendering of Large Time-Varying Volume Data

Interactive visualization of large time-varying 3D volume datasets has been and still is a great challenge to the modem computational world. It stretches the limits of the memory capacity, the disk space, the network bandwidth and the CPU speed of a conventional computer. In this SURF project, we propose to develop a parallel volume rendering program on SGI's Prism, a cluster computer equipped with state-of-the-art graphic hardware. The proposed program combines both parallel computing and hardware rendering in order to achieve an interactive rendering rate. We use 3D texture mapping and a hardware shader to implement 3D volume rendering on each workstation. We use SGI's VisServer to enable remote rendering using Prism's graphic hardware. And last, we will integrate this new program with ParVox, a parallel distributed visualization system developed at JPL. At the end of the project, we Will demonstrate remote interactive visualization using this new hardware volume renderer on JPL's Prism System using a time-varying dataset from selected JPL applications.

Garbutt, Alexander E.↗

A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors

Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.

Nguyen, Kayla↗

Optically connected memory for disaggregated data centers

Recent advances in integrated photonics enable the implementation of reconfigurable, high-bandwidth, and low energy-per-bit interconnects in next-generation data centers. We propose and evaluate an Optically Connected Memory (OCM) architecture that disaggregates the main memory from the computation nodes in data centers. OCM is based on micro-ring resonators (MRRs), and it does not require any modification to the DRAM memory modules. We calculate energy consumption from real photonic devices and integrate them into a system simulator to evaluate performance. Here, our results show that (1) OCM is capable of interconnecting four DDR4 memory channels to a computing node using two fibers with 1.02 pJ energy-per-bit consumption and (2) OCM performs up to 5.5× faster than a disaggregated memory with 40G PCIe NIC connectors to computing nodes.

97 MATHEMATICS AND COMPUTING↗

Array-based, parallel hierarchical mesh refinement algorithms for unstructured meshes

In this paper, we describe an array-based hierarchical mesh refinement capability through uniform refinement of unstructured meshes for efficient solution of PDE's using finite element methods and multigrid solvers. A multi-degree, multi-dimensional and multi-level framework is designed to generate the nested hierarchies from an initial coarse mesh that can be used for a variety of purposes such as in multigrid solvers/preconditioners, to do solution convergence and verification studies and to improve overall parallel efficiency by decreasing I/O bandwidth requirements (by loading smaller meshes and in memory refinement). We also describe a high-order boundary reconstruction capability that can be used to project the new points after refinement using high-order approximations instead of linear projection in order to minimize and provide more control on geometrical errors introduced by curved boundaries.The capability is developed under the parallel unstructured mesh framework "Mesh Oriented dAtaBase" (MOAB Tautges et al. (2004)). We describe the underlying data structures and algorithms to generate such hierarchies in parallel and present numerical results for computational efficiency and effect on mesh quality. Furthermore, we also present results to demonstrate the applicability of the developed capability to study convergence properties of different point projection schemes for various mesh hierarchies and to a multigrid finite-element solver for elliptic problems.

97 MATHEMATICS AND COMPUTING↗

Autonomous image data reduction by analysis and interpretation

Image data is a critical component of the scientific information acquired by space missions. Compression of image data is required due to the limited bandwidth of the data transmission channel and limited memory space on the acquisition vehicle. This need becomes more pressing when dealing with multispectral data where each pixel may comprise 300 or more bytes. An autonomous, real time, on-board image analysis system for an exploratory vehicle such as a Mars Rover is developed. The completed system will be capable of interpreting image data to produce reduced representations of the image, and of making decisions regarding the importance of data based on current scientific goals. Data from multiple sources, including stereo images, color images, and multispectral data, are fused into single image representations. Analysis techniques emphasize artificial neural networks. Clusters are described by their outlines and class values. These analysis and compression techniques are coupled with decision making capacity for determining importance of each image region. Areas determined to be noise or uninteresting can be discarded in favor of more important areas. Thus limited resources for data storage and transmission are allocated to the most significant images.

Eberlein, Susan↗

Autonomous image data reduction by analysis and interpretation

Image data is a critical component of the scientific information acquired by space missions. Compression of image data is required due to the limited bandwidth of the data transmission channel and limited memory space on the acquisition vehicle. This need becomes more pressing when dealing with multispectral data where each pixel may comprise 300 or more bytes. An autonomous, real time, on-board image analysis system for an exploratory vehicle such as a Mars Rover is developed. The completed system will be capable of interpreting image data to produce reduced representations of the image, and of making decisions regarding the importance of data based on current scientific goals. Data from multiple sources, including stereo images, color images, and multispectral data, are fused into single image representations. Analysis techniques emphasize artificial neural networks. Clusters are described by their outlines and class values. These analysis and compression techniques are coupled with decision-making capacity for determining importance of each image region. Areas determined to be noise or uninteresting can be discarded in favor of more important areas. Thus limited resources for data storage and transmission are allocated to the most significant images.

Eberlein, Susan↗

Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications

With more scientific fields relying on neural networks (NNs) to process data incoming at extreme throughputs and latencies, it is crucial to develop NNs with all their parameters stored on-chip. In many of these applications, there is not enough time to go off-chip and retrieve weights. Even more so, off-chip memory such as DRAM does not have the bandwidth required to process these NNs as fast as the data is being produced (e.g., every 25 ns). As such, these extreme latency and bandwidth requirements have architectural implications for the hardware intended to run these NNs: 1) all NN parameters must fit on-chip, and 2) codesigning custom/reconfigurable logic is often required to meet these latency and bandwidth constraints. In our work, we show that many scientific NN applications must run fully on chip, in the extreme case requiring a custom chip to meet such stringent constraints.

Weng, Olivia↗

Navier-Stokes Computations on Commodity Computers

In this paper we discuss and demonstrate the feasibility of solving high-fidelity, nonlinear computational fluid dynamics (CFD) problems of practical interest on commodity machines, namely Pentium Pro PC's. Such calculations have now become possible due to the progress in computational power and memory of the off-the-shelf commodity computers, along with the growth in bandwidth and communication speeds of networks. A widely used CFD code known as TLNS3D, which was developed originally on large shared memory computers was selected for this effort. This code has recently been ported to massively parallel processor (MPP) type machines, where natural partitioning along grid blocks is adopted in which one or more blocks are distributed to each of the available processors. In this paper, a similar approach is adapted to port this code to a cluster of Pentium Pro computers. The message passing among the processors is accomplished through the use of standard message passing interface (MPI) libraries. Scaling studies indicate fairly high level of parallelism on such clusters of commodity machines, thus making solutions to Navier-Stokes equations for practical problems more affordable.

Vatsa, Veer N.↗

Extreme-bandwidth scalable performance-per-watt GPU architecture

A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.

97 MATHEMATICS AND COMPUTING↗

RMA-MT Benchmarks

The RMA-MT benchmarks are a suite of performance tests for multi-threaded Message Passing Interface (MPI) Remote Memory Access (RMA) implementations. The suite includes tests for bandwidth and latency with any number of threads. This suite was originally developed and release by Sandia National Laboratory. LANL modifications to the suite include a complete re-write of much of the source code, bi-directional bandwidth, and message rate tests.

Hjelm, Nathan↗

NASA Tech Briefs, June 2009

Topics covered include: Device for Measuring Low Flow Speed in a Duct, Measuring Thermal Conductivity of a Small Insulation Sample, Alignment Jig for the Precise Measurement of THz Radiation, Autoignition Chamber for Remote Testing of Pyrotechnic Devices, Microwave Power Combiners for Signals of Arbitrary Amplitude, Synthetic Foveal Imaging Technology, Airborne Antenna System for Minimum-Cycle-Slip GPS Reception, Improved Starting Materials for Back-Illuminated Imagers, Multi-Modulator for Bandwidth-Efficient Communication, Some Improvements in Utilization of Flash Memory Devices, GPS/MEMS IMU/Microprocessor Board for Navigation, T/R Multi-Chip MMIC Modules for 150 GHz, Pneumatic Haptic Interfaces, Device Acquires and Retains Rock or Ice Samples, Cryogenic Feedthrough Test Rig, Improved Assembly for Gas Shielding During Welding or Brazing, Two-Step Plasma Process for Cleaning Indium Bonding Bumps, Tool for Crimping Flexible Circuit Leads, Yb14MnSb11 as a High-Efficiency Thermoelectric Material, Polyimide-Foam/Aerogel Composites for Thermal Insulation, Converting CSV Files to RKSML Files, Service Management Database for DSN Equipment, Chemochromic Hydrogen Leak Detectors, Compatibility of Segments of Thermoelectric Generators, Complementary Barrier Infrared Detector, JPL Greenland Moulin Exploration Probe, Ultra-Lightweight Self-Deployable Nanocomposite Structure for Habitat Applications, and Room-Temperature Ionic Liquids for Electrochemical Capacitors.

Source record↗

Moment Representation of Regularized Lattice Boltzmann Methods on NVIDIA and AMD GPUs

The lattice Boltzmann method is a highly scalable Navier-Stokes solver that has been applied to flow problems in a wide array of domains. However, the method is bandwidth-bound on modern GPU accelerators and has a large memory footprint. In this paper, we present new 2D and 3D GPU implementations of two different regularized lattice Boltzmann methods, which are not only able to achieve an acceleration of ∼ 1.4 × w.r.t. reference lattice Boltzmann implementations but also reduce the memory requirements by up to 35% and 47% in 2D and 3D simulations respectively. These new approaches are evaluated on NVIDIA and AMD GPU architectures.

Valero Lara, Pedro↗

Biplex, pipelined FFT

A method of implementing a pipelined fast Fourier transform (FFT) is presented that makes full use of the elements that comprise it. For a given bandwidth and spectral resolution, this approach requires 25 percent less memory, and needs only half the logic speed required for the conventional implementation. Since the spectrum is broken into two parts, two analog-to-digital converters, and attendant mixer-filters, are needed. These two input elements need only operate at half the speed of the one they replaced.

Emerson, R. F.↗

Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems

Graphics Processing Units (GPUs) are ubiquitous components used across the range of today’s computing plat- forms, from phones and tablets, through personal computers, to high-end server class platforms. With the increasing importance of graphics and video workloads, recent processors are shipped with GPU devices that are integrated on the same chip. Integrated GPUs share some resources with the CPU and as a result, there is a potential for microarchitectural attacks from the GPU to the CPU or vice versa. We consider the potential for covert channel attacks that arise either from shared microarchitectural components (such as caches) or through shared contention domains (e.g., shared buses). We illustrate these two types of channels by developing two reliable covert channel attacks. The first covert channel uses the shared LLC cache in Intel’s integrated GPU architectures. The second is a contention based channel targeting the ring bus connecting the CPU and GPU to the LLC. This is the first demonstrated microarchitectural attack crossing the component boundary (GPU to CPU or vice versa). Cross-component channels introduce a number of new challenges that we had to overcome since they occur across heterogeneous components that use different computation models and are interconnected using asymmetric memory hierarchies. We also exploit GPU parallelism to increase the bandwidth of the communication, even without relying on a common clock. The LLC based channel achieves a bandwidth of 120 kbps with a low error rate of 2%, while the contention based channel delivers up to 400 kbps with a 0.8% error rate. We also demonstrate a proof- of-concept prime-and-probe side channel attack that probes the full LLC from the GPU.

Cyber secruity, high performance comptuing, Hetero↗

Optimal strategies for optical quantum memories using long-lived noble-gas spins

Nuclear spins of noble gases exhibit exceptionally long coherence times and can potentially serve as a long-lived storage medium for quantum information. We analyze and compare the performance of two mechanisms for mapping the quantum state of light onto the collective spin state of noble gases. The first mechanism utilizes collisional exchange with the electronic spin state of metastable noble-gas atoms, while the second relies on spin-exchange collisions with ground-state alkali-metal atoms. We describe the operation of an optical quantum memory relying on these two mechanisms using a compact model and study strategies that optimize the memory storage efficiency. Through numerical simulations, we identify optimal sequences for storing optical signals with different signal bandwidths and electronic spin relaxation rates. This work highlights the qualitative difference between the two approaches for using noble gases as long-lived quantum memories at noncryogenic conditions and outlines the regimes in which they are expected to be efficient.

atomic ensemble↗