Search NASA⌕ Search

SEARCH · Search NASA

Results for “Onboard processing”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 181 records · Page 10

Image processing using Gallium Arsenide (GaAs) technology

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Miller, Warner H.↗

Modulation and synchronization technique for MF-TDMA system

This report addresses modulation and synchronization techniques for a multi-frequency time division multiple access (MF-TDMA) system with onboard baseband processing. The types of synchronization techniques analyzed are asynchronous (conventional) TDMA, preambleless asynchronous TDMA, bit synchronous timing with a preamble, and preambleless bit synchronous timing. Among these alternatives, preambleless bit synchronous timing simplifies onboard multicarrier demultiplexer/demodulator designs (about 2:1 reduction in mass and power), requires smaller onboard buffers (10:1 to approximately 3:1 reduction in size), and provides better frame efficiency as well as lower onboard processing delay. Analysis and computer simulation illustrate that this technique can support a bit rate of up to 10 Mbit/s (or higher) with proper selection of design parameters. High bit rate transmission may require Doppler compensation and multiple phase error measurements. The recommended modulation technique for bit synchronous timing is coherent QPSK with differential encoding for the uplink and coherent QPSK for the downlink.

Faris, Faris↗

Optical data processing study

An onboard coherent optical data processing system was designed to handle large information content of imagery at high speeds, reduce redundancy in picture transmission, and detect specific image features. Theoretically derived Fourier transform characteristics for simple but representative two dimensional images served as a basis for predicting expected features of actual target images. Fourier transformation and spatial filtering of coherent optical images was accomplished theoretically and in the laboratory. The effect of various parameters such as optical aperature, incidence angles, the transparency assumption, the thin lens approximation on resolution, and performance of the system are predicted and tested.

Pinson, L. J.↗

International Space Station Noise Constraints Flight Rule Process

Crewmembers onboard the International Space Station (ISS) live in a unique workplace environment for as long as 6 ‐12 months. During these long‐duration ISS missions, noise exposures from onboard equipment are posing concerns for human factors and crewmember health risks, such as possible reductions in hearing sensitivity, disruptions of crew sleep, interference with speech intelligibility and voice communications, interference with crew task performance, and reduced alarm audibility. The purpose of this poster is to describe how a recently‐updated noise constraints flight rule is being used to implement a NASA‐created Noise Exposure Estimation Tool and Noise Hazard Inventory to predict crew noise exposures and recommend when hearing protection devices are needed.

Limardo, Jose G.↗

High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors

Exponential growth in microelectronics technology such as field-programmable gate arrays (FPGAs) has enabled high-performance spaceborne instruments with increasing onboard data processing capabilities. As a commonly used digital signal processing (DSP) building block, fast Fourier transform (FFT) has been of great interest in onboard data processing applications, which needs to strike a reasonable balance between high-performance (throughput, block size, etc.) and low resource usage (power, silicon footprint, etc.). It is also desirable to be designed so that a single design can be reused and adapted into instruments with different requirements. The Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture was developed, in which the high-throughput benefits of the parallel FFT structure and the low resource usage of Singleton s single butterfly method is exploited. The result is a wide-kernel, multipass, adaptive FFT architecture. The 32K-point MPWK-FFT architecture includes 32 radix-2 butterflies, 64 FIFOs to store the real inputs, 64 FIFOs to store the imaginary inputs, complex twiddle factor storage, and FIFO logic to route the outputs to the correct FIFO. The inputs are stored in sequential fashion into the FIFOs, and the outputs of each butterfly are sequentially written first into the even FIFO, then the odd FIFO. Because of the order of the outputs written into the FIFOs, the depth of the even FIFOs, which are 768 each, are 1.5 times larger than the odd FIFOs, which are 512 each. The total memory needed for data storage, assuming that each sample is 36 bits, is 2.95 Mbits. The twiddle factors are stored in internal ROM inside the FPGA for fast access time. The total memory size to store the twiddle factors is 589.9Kbits. This FFT structure combines the benefits of high throughput from the parallel FFT kernels and low resource usage from the multi-pass FFT kernels with desired adaptability. Space instrument missions that need onboard FFT capabilities such as the proposed DESDynl, SWOT (Surface Water Ocean Topography), and Europa sounding radar missions would greatly benefit from this technology with significant reductions in non-recurring cost and risk.

NguyenKobayashi, Kayla↗

Onboard Classification of Hyperspectral Data on the Earth Observing One Mission

Remote-sensed hyperspectral data represents significant challenges in downlink due to its large data volumes. This paper describes a research program designed to process hyperspectral data products onboard spacecraft to (a) reduce data downlink volumes and (b) decrease latency to provide key data products (often by enabling use of lower data rate communications systems). We describe efforts to develop onboard processing to study volcanoes, floods, and cryosphere, using the Hyperion hyperspectral imager and onboard processing for the Earth Observing One (EO-1) mission as well as preliminary work targeting the Hyperspectral Infrared Imager (HyspIRI) mission.

cryosphere↗

Onboard high data rate signal processing and storage

The objective is to advance the state of the art in onboard image data processing and storage through the use of advanced gallium arsenide integrated circuit technology. Viewgraphs are given on research and development efforts, an adaptive programmable processor chip set, design characteristics of an eight bit general processor, and a density comparison of silicon and gallium arsenide integrated circuits.

Miller, Warner H.↗

A CCD image transducer and processor suitable for space flight

A satellite borne extreme ultraviolet solar telescope makes use of CCD area arrays for both image readout and onboard data processing. The instrument is designed to view the inner solar corona in the wavelength band 170 - 630 A, and the output video stream may be selected by ground command to present the coronal scene, or the time-rate-of-change of the scene. Details of the CCD application to onboard image processing are described, and a discussion of the processor's potential for telemetry bandwidth compression is included. Optical coupling methods, data storage requirements, spatial and temporal resolution, and nonsymmetry of resolution (pitch) in the CCD are discussed.

Michels, D. J.↗

Packet communications in satellites with multiple-beam antennas and signal processing

A communication satellite with a multiple-beam antenna and onboard signal processing is considered for use in a 'message-switched' data relay system. The signal processor may incorporate demodulation, routing, storage, and remodulation of the data. A system user model is established and key functional elements for the signal processing are identified. With the throughput and delay requirements as the controlled variables, the hardware complexity, operational discipline, occupied bandwidth, and overall user end-to-end cost are estimated for (1) random-access packet switching; and (2) reservation-access packet switching. Other aspects of this network (eg, the adaptability to channel switched traffic requirements) are examined. For the given requirements and constraints, the reservation system appears to be the most attractive protocol.

Davies, R.↗

On-board multispectral classification study

The factors relating to onboard multispectral classification were investigated. The functions implemented in ground-based processing systems for current Earth observation sensors were reviewed. The Multispectral Scanner, Thematic Mapper, Return Beam Vidicon, and Heat Capacity Mapper were studied. The concept of classification was reviewed and extended from the ground-based image processing functions to an onboard system capable of multispectral classification. Eight different onboard configurations, each with varying amounts of ground-spacecraft interaction, were evaluated. Each configuration was evaluated in terms of turnaround time, onboard processing and storage requirements, geometric and classification accuracy, onboard complexity, and ancillary data required from the ground.

Ewalt, D.↗

Experiment in Onboard Synthetic Aperture Radar Data Processing

Single event upsets (SEUs) are a threat to any computing system running on hardware that has not been physically radiation hardened. In addition to mandating the use of performance-limited, hardened heritage equipment, prior techniques for dealing with the SEU problem often involved hardware-based error detection and correction (EDAC). With limited computing resources, software- based EDAC, or any more elaborate recovery methods, were often not feasible. Synthetic aperture radars (SARs), when operated in the space environment, are interesting due to their relevance to NASAs objectives, but problematic in the sense of producing prodigious amounts of raw data. Prior implementations of the SAR data processing algorithm have been too slow, too computationally intensive, and require too much application memory for onboard execution to be a realistic option when using the type of heritage processing technology described above. This standard C-language implementation of SAR data processing is distributed over many cores of a Tilera Multicore Processor, and employs novel Radiation Hardening by Software (RHBS) techniques designed to protect the component processes (one per core) and their shared application memory from the sort of SEUs expected in the space environment. The source code includes calls to Tilera APIs, and a specialized Tilera compiler is required to produce a Tilera executable. The compiled application reads input data describing the position and orientation of a radar platform, as well as its radar-burst data, over time and writes out processed data in a form that is useful for analysis of the radar observations.

Holland, Matthew↗

On-board switching and processing

Findings from NASA's space electronics division's (SED's) advanced systems studies related to future communications satellite services that will require onboard switching and processing technology are reviewed. SED's digital signal switching and processing technology program is reviewed. This program responds to specific systems technology development needs for enabling commercial development of future satellite services. The technologies include: modulators, demodulators, and forward error-correction hardware for space- and ground-based applications; onboard information switching and processing, onboard network control, and health monitoring; and cost-efficient ground terminals. The in-house systems integration, test, and evaluation (SITE) project, which includes a laboratory testbed for evaluating technology in a simulated systems environment, is reviewed.

Harrold, Joseph L.↗

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.↗

Estimating Dust and Water Ice Content of the Martian Atmosphere From THEMIS Data

Researchers at JPL and Arizona State University conducted a comparative study of three candidate algorithms for estimating components of the Martian atmosphere, using raw (uncalibrated) data collected by the Thermal Emission Imaging System (THEMIS). THEMIS is an instrument onboard the Mars Odyssey spacecraft that acquires image data in five visible and nine infrared (IR) wavelength bands. The algorithms under study used data collected from eight of the nine IR bands to estimate the dust and water ice content of the atmosphere. Such an algorithm could be used in onboard data processing to trigger other algorithms that search for features of scientific interest and to reduce the volume of data transmitted to Earth. The algorithms studied were based on regression models. In the study, the optical depths estimated by these algorithms were compared with optical depths estimated in ground-based processing using fully calibrated data from both THEMIS and the Thermal Emission Spectrometer (TES). TES is an instrument onboard the Mars Global Surveyor spacecraft that also observes the planet at infrared wavelengths, but at a lower spatial resolution than THEMIS does. Of the algorithms studied, the one that performed best was based on a Gaussian Support Vector Machine regression model. The test results indicated that this algorithm, operating on the raw data, had error rates that were within the uncertainty associated with the estimates obtained by the groundbased analysis of the fully calibrated data. This level of fidelity demonstrates that these algorithms are sufficiently accurate for use in an onboard setting.

Bandfield, Joshua↗

Fault-Tolerant, Radiation-Hard DSP

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Czajkowski, David↗