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Heavy-ion radiation effects knowledge across SiC power devices is examined and insights for more rugged designs and appropriate test methods geared toward space applications are extracted. The conclusions drawn are supported by recent publicly reported heavy-ion test results of a modified SiC MOSFET design.
The performance of two multi-element, multiplexed Ge:Ga linear arrays under low-background conditions was investigated. The on-focal switching is accomplished by MOSFET switches, and the integrated charge is made available through MOSFET source followers. The tests were conducted at 106 microns, and the radiation on the detectors was confined to a spectral window 1.25 microns wide using a stack of cold filters. At 4.2 K, the highest responsivity was 584 A/W, the noise equivalent power was 1.0 x 10(exp -16) W/square root of Hz, and the read noise was 6100 electrons/sample. A detailed description of the test setup and procedure is presented.
Irradiation of several low power circuit elements by Co-60 gamma radiation, low and high energy electrons, and neutrons is discussed. The bipolar circuits were SE480 Q NAND gate, and a micropower frequency divider was used in electronic wrist watches. The MOS device was a dual p-channel MOSFET.
An Infrared Camera was built for astronomical observations and for testing arrays for satellite based work. The detectors are sensitive to mid infrared wavelengths. The camera was tested at the University of Arizona 61 and 90 inch telescopes and the NASA IRTF. These tests have demonstrated a sensitivity consistent with photon shot noise with an approximately 10% quantum efficiency for each pixel when the camera was used with a 1.6% spectral filter or when used with a Fabry-Perot having a resolving power of 2000. Initial measurements of read out noise, dark current, cross talk, and hysteresis were made. The detector chip in current use is a hybrid array manufactured by the Hughes Aircraft Company. Because part of the goal was to develop and advance technology, it was decided to work with a switched MOSFET array. This architecture is very promising, and the detector parameters will be quantified carefully.
A series-connected buck boost regulator (SCBBR) is an electronic circuit that bucks a power-supply voltage to a lower regulated value or boosts it to a higher regulated value. The concept of the SCBBR is a generalization of the concept of the SCBR, which was reported in "Series-Connected Boost Regulators" (LEW-15918), NASA Tech Briefs, Vol. 23, No. 7 (July 1997), page 42. Relative to prior DC-voltage-regulator concepts, the SCBBR concept can yield significant reductions in weight and increases in power-conversion efficiency in many applications in which input/output voltage ratios are relatively small and isolation is not required, as solar-array regulation or battery charging with DC-bus regulation. Usually, a DC voltage regulator is designed to include a DC-to-DC converter to reduce its power loss, size, and weight. Advances in components, increases in operating frequencies, and improved circuit topologies have led to continual increases in efficiency and/or decreases in the sizes and weights of DC voltage regulators. The primary source of inefficiency in the DC-to-DC converter portion of a voltage regulator is the conduction loss and, especially at high frequencies, the switching loss. Although improved components and topology can reduce the switching loss, the reduction is limited by the fact that the converter generally switches all the power being regulated. Like the SCBR concept, the SCBBR concept involves a circuit configuration in which only a fraction of the power is switched, so that the switching loss is reduced by an amount that is largely independent of the specific components and circuit topology used. In an SCBBR, the amount of power switched by the DC-to-DC converter is only the amount needed to make up the difference between the input and output bus voltage. The remaining majority of the power passes through the converter without being switched. The weight and power loss of a DC-to-DC converter are determined primarily by the amount of power processed. In the SCBBR, the unswitched majority of the power is passed through with very little power loss, and little if any increase in the sizes of the converter components is needed to enable the components to handle the unswitched power. As a result, the power-conversion efficiency of the regulator can be very high, as shown in the example of Figure 1. A basic SCBBR includes a DC-to-DC converter (see Figure 2). The switches and primary winding of a transformer in the converter is connected across the input bus, while the secondary winding and switches are connected in series with the output bus, so that the output voltage is the sum of the input voltage and the secondary voltage of the converter. In the breadboard SCBBR, the input voltage applied to the primary winding is switched by use of metal oxide/semiconductor field-effect transistors (MOSFETs) in a full bridge circuit; the secondary winding is center-tapped, with two MOSFET switches and diode rectifiers connected in opposed series in each leg. The sets of opposed switches and rectifiers are what enable operation in either a boost or a buck mode. In the boost mode, input voltage and current, and the output voltage and current are all positive; that is, the secondary voltage is added to the input voltage and the net output voltage can be regulated at a value equal or greater than the input voltage. In the buck mode, input voltage is still positive and the current still flows in the same direction in the secondary, but the switches are controlled such that some power flows from the secondary to the primary. The voltage across the secondary and the current into the primary are reversed. The result is that the output voltage is lower than the input voltage, and some power is recirculated from the converter secondary back to the input. Quantitatively, the advantage of an SCBBR is a direct function of the regulation range required. If, for example, a regulation range of 20 percent is required for a 500-W supply, th it suffices to design the DC-to-DC converter in the SCBBR for a power rating of only 100 W. The switching loss and size are much smaller than those of a conventional regulator that must be rated for switching of all 500 W. The reduction in size and the increase in efficiency are not directly proportional to switched-power ratio of 5:1 because the additional switches contribute some conduction loss and the input and output filters must be larger than those typically required for a 100-W converter. Nevertheless, the power loss and the size can be much smaller than those of a 500-W converter.
NASA's X-57 all-electric aircraft was a research project aimed at investigating lightweight and efficient electric propulsion components. The general approach was to utilize a distributed electric propulsion (DEP) design. An essential component of this design was the High Lift Motor Controller (HLMC), a motor drive which provided power to the High Lift Motors (HLMs) and High Lift Propellers (HLPs) responsible for providing additional thrust for take-off and landing. This paper presents the detailed design, test results, and outcomes from the development of the HLMC, a 14 kW, 1kg, 98.3% efficient, outer mold line (OML) cooled, silicon carbide (SiC) MOSFET-based inverter and controller.
NASA's X-57 all-electric aircraft was a research project aimed at investigating lightweight and efficient electric propulsion components. The general approach was to utilize a distributed electric propulsion (DEP) design. An essential component of this design was the High Lift Motor Controller (HLMC), a motor drive which provided power to the High Lift Motors (HLMs) and High Lift Propellers (HLPs) responsible for providing additional thrust for take-off and landing. This paper presents the detailed design, test results, and outcomes from the development of the HLMC, a 14 kW, 1kg, 98.3% efficient, outer mold line (OML) cooled, silicon carbide (SiC) MOSFET-based inverter and controller.
There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported.
After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.
After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the area of crystal growth and device fabrication technology. High quality of single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.
The design and performance of a prototype power-conditioning system for use with large brushless dc motors on NASA space missions are discussed in detail and illustrated with extensive diagrams, drawings, and graphs. The 5-kW 8-phase parallel module evaluated here would be suitable for use in the Space Shuttle Orbiter cargo bay. A current-balancing magnetic assembly with low distributed inductance permits high-speed current switching from a low-voltage bus as well as current balancing between parallel MOSFETs.
CUBESATS are relatively new spacecraft platforms that are typically deployed from a launch vehicle as a secondary payload,1 providing low-cost access to space for a wide range of end-users. These satellites are comprised of building blocks having dimensions of 10x10x10 cm cu and a mass of 1.33 kg (a 1-U size). While providing low-cost access to space, a major operational limitation is the lack of a propulsion system that can fit within a CubeSat and is capable of executing high delta v maneuvers. This makes it difficult to use CubeSats on missions requiring certain types of maneuvers (i.e. formation flying, spacecraft rendezvous). Recently, work has been performed investigating the use of iodine as a propellant for Hall-effect thrusters (HETs) 2 that could subsequently be used to provide a high specific impulse path to CubeSat propulsion. Iodine stores as a dense solid at very low pressures, making it acceptable as a propellant on a secondary payload. It has exceptionally high ρIsp (density times specific impulse), making it an enabling technology for small satellite near-term applications and providing the potential for systems-level advantages over mid-term high power electric propulsion options. Iodine flow can also be thermally regulated, subliming at relatively low temperature ( less than100 C) to yield I2 vapor at or below 50 torr. At low power, the measured performance of an iodine-fed HET is very similar to that of a state-of-the-art xenon-fed thruster. Just as importantly, the current-voltage discharge characteristics of low power iodine-fed and xenon-fed thrusters are remarkably similar, potentially reducing development and qualifications costs by making it possible to use an already-qualified xenon-HET PPU in an iodine-fed system. Finally, a cold surface can be installed in a vacuum test chamber on which expended iodine propellant can deposit. In addition, the temperature doesn't have to be extremely cold to maintain a low vapor pressure in the vacuum chamber (it is under 10(exp -6) torr at -75 C), making it possible to 'cryopump' the propellant with lower-cost recirculating refrigerant-based systems as opposed to using liquid nitrogen or low temperature gaseous helium cryopanels. In the present paper, we describe testing performed using an iodine-fed 200 W Hall thruster mounted to a thrust stand and operated in conjunction with MSFCs Small Projects Rapid Integration and Test Environment (SPRITE) Portable Hardware In the Loop (PHIL) hardware. This work is performed in support of the iodine satellite (iSAT) project, which aims to fly a 200-W iodine-fed thruster on a 12-U CubeSat. The SPRITE PHIL hardware allows a given vehicle to do a checkout of its avionics algorithm by allowing it to monitor and feed data to simulated sensors and effectors in a digital environment. These data are then used to determine the attitude of the vehicle and a separate computer is used to interpret the data set and visualize it using a 3D graphical interface. The PHIL hardware allows the testing of the vehicles bus by providing 'real' hardware interfaces (in the case of this test a real RS422 bus) and specific components can be modeled to show their interactions with the avionics algorithm (e.g. a thruster model). For the iSAT project the PHIL is used to visualize the operating cycle of the thruster and the subsequent effect this thrusting has on the attitude of the satellite over a given period of time. The test is controlled using software running on an Andrews Space Cortex 160 flight computer. This computer is the current baseline for a full iSAT mission. While the test could be conducted with a lab computer and software, the team chose to exercise the propulsion system with a representative CubeSat-class computer. For purposes of this test, the "flight" software monitored the propulsion and PPU systems, controlled operation of the thruster, and provided thruster state data to the PHIL simulation. Commands to operate the thruster were initiated from an operator's workstation outside the vacuum chamber and passed through the Cortex 160 to exercise portions of the flight avionics. Two custom-designed pieces of electronics hardware have been designed to operate the propellant feed system. One piece of hardware is an auxiliary board that controls a latch valve, proportional flow control valves (PFCVs) and valve heaters as well as measuring pressures, temperatures and PFCV feedback voltage. An onboard FPGA provides a serial link for issuing commands and manages all lower level input-output functions. The other piece of hardware is a power distribution board, which accepts a standard bus voltage input and converts this voltage into all the different current-voltage types required to operate the auxiliary board. These electronics boards are located in the vacuum chamber near the thruster, exposing this hardware to both the vacuum and plasma environments they would encounter during a mission, with these components communicating to the flight computer through an RS-422 interface. The auxiliary board FPGA provides a 28V MOSFET switch circuit with a 20ms pulse to open or close the iodine propellant feed system latch valve. The FPGA provides a pulse width modulation (PWM) signal to a DC/DC boost converter to produce the 12-120V needed for control of the proportional flow control valve. There are eight MOSFET-switched heating circuits in the system. Heaters are 28V and located in the latch valve, PFCV, propellant tank and propellant feed lines. Both the latch valve and PFCV have thermistors built into them for temperature monitoring. There are also seven resistance temperature device (RTD) circuits on the auxiliary board that can be used to measure the propellant tank and feedline temperatures. The signals are conditioned and sent to an analog to digital converter (ADC), which is directly commanded and controlled by the FPGA.
Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.
Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.
Low-frequency, low-noise, low-power cryogenic electronics to read out photodetectors is being investigated for the star-tracking telescope of the Gravity Probe B spacecraft. We report our initial findings from evaluating more than 20 types of GaAs FETs, both commercial and non-commercial, for this application. Most exhibit useable dc characteristics at cryogenic temperatures, although gate leakage and hysteretic effects (presumably due to charge trapping) could be troublesome. Low-frequency noise (based primarily on grounded-gate measurements) at 4 K is '1/f-like' and for the quietest GaAs FETs appears to be at least as low as the lowest noise values reported for Si MOSFETs at 4 K. Further investigation is needed in several areas.
This report describes the investigation of growth properties, and the structure of epitaxial multilayer Si(Si(1x)Ge(x)) films grown on bulk Silicon Substrates. It also describes the fabrication and characterization of MOSFET and MESFET devices made on these epitaxial films. Films were grown in a CVD reactor using hydrides of Si and Ge with H2 and He as carrier gases. Growth temperatures were between 900 C and 1050 C with most films grown at 1000 C. Layer thickness was between 300A and 2000A and total film thickness was between 0.25 micro m and 7 micro m. The Ge content (X) in the alloy layers was between .05 and 0.2. N-type multilayer films grown on (100) p-type Si showed Hall mobility in the range 1000 to 1500 sq cm/v for an average carrier concentration of approx. 10 to the 16th power/cu cm. This is up to 50% higher than the Hall mobility observed in epitaxial Si films grown under the same conditions and with the same average carrier concentration. The mobility enhancement occurred in films with average carrier concentration (n) from 0.7 x 10 to the 16th power to 2 x 10 to the 17th power/cu cm, and total film thickness greater than 1.0 micro m. No mobility enhancement was seen in n-type multilayer films grown on (111) Si or in p-type multilayer films. The structure of the films was investigated was using SEM, TEM, AES, SIMS, and X-ray double crystal diffraction techniques. The film composition profile (AES, SIMS) showed that the transition region between layers is of the order of about 100A. The TEM examination revealed a well defined layered structure with fairly sharp interfaces and good crystalline quality. It also showed that the first few layers of the film (closest to the substrate) are uneven, most probably due to the initial growth pattern of the epitaxial film where growth occurs first in isolated islands that eventually growth and coalesce. The X-ray diffraction measurement determined the elastic strain and strain relief in the alloy layers of the film and the elastic strain in the intervening Si layers.
This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.
The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active natural clamped converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic cancelling effect, and DC-link capacitor placement. The loop inductance of the designed busbar is verified with simulation, impedance measurements and converter experiment. The results can match with each other and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.