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At least 181 records · Page 10

Design of Timer Circuit for Dynamic Data System

The Branch That I work in is in the Aero Electronic Test Branch, which is part of the Research and Testing Division. The Aero Electronic Test Branch deals with electronic control and instrumentation systems. This branch supports the research and test study of wind tunnels such as the l0x10,9x15, and 8x6. Wind tunnels are used in research to test certain parts of a jet, plane, shuttle or any other flying object in certain test conditions. My assignment is to design a programmable trigger circuit on a 19 standard rack mount that will allow the circuit to latch and hold for a predefined amount of time entered by the user when receiving a signal. It should then re-arm itself within 0.25 seconds after the time is finished. The time should be able to be seen on a display showing the time entered. The time range has to be from 0-600 seconds in 0.01 second increments (600.00). From the information given, counters will be needed to design and build this circuit. A counter, in it s simplest form, is a group of flip flops that can temporarily store bits of information put into the circuit. They can be constructed in many different ways, such as in 4 flip flops (4-bit counter) or 8 flip flops and even higher. Counters are usually cascaded with other counters to reach higher bits, such as 16 or 24 bit counters. The application in which I will use the counters will be to count down from any programmable number that I input either by a keyboard or a thumbwheel. Also, I will use counters that will be used specifically as a frequency divider to divide the pulses that enter the circuit through an input signal from a crystal clock. The pulses will need to be divided so that it will function as a 100Hz clock putting out 100 pulses per second. A switch will be used to load my inputs in and more than likely a button also so that I can stop and hold the count at any point of time. I will use 5 BCD up/down programmable counters, and a certain amount (depending on what kind of "divide by N" counter I use) of frequency dividing counters for the assignment. After the design is carefully made, a task order will be written and then given to the manufacturer to create a rack mount circuit board that will match my specifications given. The applications in which this design will be used for is in the use of the six-component balance signal conditioner for measurement and electronic system control. It can be used as a timer system for the balance signal conditioner in which it does numerous tests for the Wind tunnel research, in which a preset time can be set for how long it performs its tests. Specifically, my design should be applied to the balance signal conditioner used for the 8x6 wind tunnel research. Hopefully this design should aid in more efficient research for the 8x6 wind tunnel.

Young, Nathaniel, III↗

Synchronizing Light Pulses With Video Camera

Interface circuit triggers laser or other external source of light to flash in proper frame and field (at proper time) for video recording and playback in "pause" mode. Also increases speed of electronic shutter (if any) during affected frame to reduce visibility of background illumination relative to that of laser illumination.

Kalshoven, James E., Jr.↗

Detonation to Deflagration-Mode Transitions in Pulsed Plasma Accelerators

PULSED plasma accelerators typically operate by storing energy in a capacitor bank and then discharging this energy through a gas. The current in such discharges will ionize the gas and produce a strong magnetic field, which interacts with the flowing current to accelerate the plasma through the Lorentz body force. For the present work, two plasma accelerator types employing this general scheme are of interest: the gas-fed pulsed plasma thruster (PPT) 1 and the quasi-steady magnetoplasmadynamic (MPD) accelerator. 2 The gas-fed pulsed plasma accelerator is generally understood as a completely transient device discharging in ∼1-10 μs. When the capacitor bank is discharged through the gas, a current sheet forms at the breech of the thruster and propagates forward under a j × B body force, entraining and accelerating propellant it encounters. This process is sometimes referred to in literature as 'snowplowing' the propellant or accelerating the gas in a detonation-mode because the current sheet representation approximates that of a strong detonation shockwave propagating through the gas. For these devices, acceleration of the initial current sheet ceases when either the current sheet reaches the end of the device and is ejected or when the current in the circuit reverses, striking a new 'crowbar' discharge at the breech and depriving the initial sheet of additional acceleration. In general, PPTs typically claim thrust efficiencies (ratio of jet kinetic energy to input electrical energy) registering in the teens or lower. 3 In the quasi-steady MPD accelerator, the pulse is lengthened to ∼1 ms or longer and maintained at an approximately constant level during discharge through the use of a pulse-forming network (PFN) of capacitors. After an initial transient discharge, which is typically short relative to the overall discharge period, the plasma assumes a relatively steady-state configuration, known as 'quasi-steady' MPD operation. 2 In this state, ionized gas flows through a stationary current channel in a manner that is sometimes referred to as deflagration-mode operation owing to the similarities to deflagration waves in gases. The plasma experiences electromagnetic acceleration as the plasma flows through the current channel towards the exit of the device. Quasi-steady MPD thrusters claim efficiencies up to 50% for certain propellants.4 There has been significant and sustained research over several decades on both gas-fed PPTs and quasi-steady MPD thrusters, however there have been pulsed thrusters that do not appear to exactly fit either classification, instead possessing a mixture of operational qualities characteristic of both thruster variants. The Coaxial High ENerGy (CHENG) thruster by Cheng, et al.5 operated on the short 10 μs timescales characteristic of PPTs, but claimed the high thrust densities, high efficiencies, and low electrode erosion rates that are more consistent with the MPD/deflagration mode of plasma acceleration. Gas-fed PPT research by Ziemer, et al. 3, 6 identified two separate regimes of performance in those thrusters. The regime at higher mass bits (termed Mode I in that work) possessed relatively constant thrust efficiency as a function of mass bit, while the second regime at very low mass bits (termed Mode II) exhibited an increase in efficiency with decreasing mass bit. Work by Poehlmann et al.7 and by Sitaraman and Raja8 sought to understand the performance of the CHENG thruster and the Mode I/Mode II performance in PPTs by modeling the acceleration using the Hugoniot Relation, with the detonation and deflagration modes of plasma acceleration representing two distinct sets of solutions to the relevant conservation laws. In these works, it was proposed that the values of the various controllable parameters determined whether the accelerator would operate in detonation or deflagration mode. Our hypothesized view of the acceleration process in the CHENG thruster and in PPTs experiencing a transition from Mode I to Mode II is inspired by observations of the transition from the PPT mode of operation to the quasi-steady MPD mode. Specifically, the quasi-steady MPD was discovered by driving a PPT to extended pulse lengths. Above a certain pulse length threshold the transient plasma current sheet transitions into a stable plasma acceleration mode that 'replicates in every observable detail steady flow self-field magnetoplasmadynamic acceleration.' 9 In the present work, instead of treating the accelerator as if it were only operating in a single mode during a pulse, we consider the initial stage of the discharge in all cases as a current sheet forming at the breach of the accelerator and moving towards the exit as a detonation wave. If the current sheet reaches the exit of the accelerator before the discharge is completed, the view of the acceleration mode transitions to the deflagration mode-type found in quasi-steady MPD thrusters. In previous work10 we presented a modeling framework that first captured the time-evolution of the current sheet (detonation) mode of the thruster and then transitioned into the quasi-steady MPD (deflagration) mode of plasma acceleration. In the present work, variations of the controllable parameters - specifically the pulsed circuit properties, the amount of mass injected into the thruster, and the relative timing between the initial gas injection and the initiation of the plasma current sheet - will be used to explore the thruster performance. A range of parameters are explored to demonstrate that standard gas-fed pulsed plasma accelerators, the CHENG thruster, and the quasi-steady MPD accelerator are variations of the same device, with the overall acceleration of the plasma depending upon the behavior of the plasma discharge during initial transient phase and the relative lengths of the detonation and deflagration modes of operation.

Polzin, Kurt A.↗

Hardware in the Loop Testing of an Iodine-Fed Hall Thruster

CUBESATS are relatively new spacecraft platforms that are typically deployed from a launch vehicle as a secondary payload,1 providing low-cost access to space for a wide range of end-users. These satellites are comprised of building blocks having dimensions of 10x10x10 cm cu and a mass of 1.33 kg (a 1-U size). While providing low-cost access to space, a major operational limitation is the lack of a propulsion system that can fit within a CubeSat and is capable of executing high delta v maneuvers. This makes it difficult to use CubeSats on missions requiring certain types of maneuvers (i.e. formation flying, spacecraft rendezvous). Recently, work has been performed investigating the use of iodine as a propellant for Hall-effect thrusters (HETs) 2 that could subsequently be used to provide a high specific impulse path to CubeSat propulsion. Iodine stores as a dense solid at very low pressures, making it acceptable as a propellant on a secondary payload. It has exceptionally high ρIsp (density times specific impulse), making it an enabling technology for small satellite near-term applications and providing the potential for systems-level advantages over mid-term high power electric propulsion options. Iodine flow can also be thermally regulated, subliming at relatively low temperature ( less than100 C) to yield I2 vapor at or below 50 torr. At low power, the measured performance of an iodine-fed HET is very similar to that of a state-of-the-art xenon-fed thruster. Just as importantly, the current-voltage discharge characteristics of low power iodine-fed and xenon-fed thrusters are remarkably similar, potentially reducing development and qualifications costs by making it possible to use an already-qualified xenon-HET PPU in an iodine-fed system. Finally, a cold surface can be installed in a vacuum test chamber on which expended iodine propellant can deposit. In addition, the temperature doesn't have to be extremely cold to maintain a low vapor pressure in the vacuum chamber (it is under 10(exp -6) torr at -75 C), making it possible to 'cryopump' the propellant with lower-cost recirculating refrigerant-based systems as opposed to using liquid nitrogen or low temperature gaseous helium cryopanels. In the present paper, we describe testing performed using an iodine-fed 200 W Hall thruster mounted to a thrust stand and operated in conjunction with MSFCs Small Projects Rapid Integration and Test Environment (SPRITE) Portable Hardware In the Loop (PHIL) hardware. This work is performed in support of the iodine satellite (iSAT) project, which aims to fly a 200-W iodine-fed thruster on a 12-U CubeSat. The SPRITE PHIL hardware allows a given vehicle to do a checkout of its avionics algorithm by allowing it to monitor and feed data to simulated sensors and effectors in a digital environment. These data are then used to determine the attitude of the vehicle and a separate computer is used to interpret the data set and visualize it using a 3D graphical interface. The PHIL hardware allows the testing of the vehicles bus by providing 'real' hardware interfaces (in the case of this test a real RS422 bus) and specific components can be modeled to show their interactions with the avionics algorithm (e.g. a thruster model). For the iSAT project the PHIL is used to visualize the operating cycle of the thruster and the subsequent effect this thrusting has on the attitude of the satellite over a given period of time. The test is controlled using software running on an Andrews Space Cortex 160 flight computer. This computer is the current baseline for a full iSAT mission. While the test could be conducted with a lab computer and software, the team chose to exercise the propulsion system with a representative CubeSat-class computer. For purposes of this test, the "flight" software monitored the propulsion and PPU systems, controlled operation of the thruster, and provided thruster state data to the PHIL simulation. Commands to operate the thruster were initiated from an operator's workstation outside the vacuum chamber and passed through the Cortex 160 to exercise portions of the flight avionics. Two custom-designed pieces of electronics hardware have been designed to operate the propellant feed system. One piece of hardware is an auxiliary board that controls a latch valve, proportional flow control valves (PFCVs) and valve heaters as well as measuring pressures, temperatures and PFCV feedback voltage. An onboard FPGA provides a serial link for issuing commands and manages all lower level input-output functions. The other piece of hardware is a power distribution board, which accepts a standard bus voltage input and converts this voltage into all the different current-voltage types required to operate the auxiliary board. These electronics boards are located in the vacuum chamber near the thruster, exposing this hardware to both the vacuum and plasma environments they would encounter during a mission, with these components communicating to the flight computer through an RS-422 interface. The auxiliary board FPGA provides a 28V MOSFET switch circuit with a 20ms pulse to open or close the iodine propellant feed system latch valve. The FPGA provides a pulse width modulation (PWM) signal to a DC/DC boost converter to produce the 12-120V needed for control of the proportional flow control valve. There are eight MOSFET-switched heating circuits in the system. Heaters are 28V and located in the latch valve, PFCV, propellant tank and propellant feed lines. Both the latch valve and PFCV have thermistors built into them for temperature monitoring. There are also seven resistance temperature device (RTD) circuits on the auxiliary board that can be used to measure the propellant tank and feedline temperatures. The signals are conditioned and sent to an analog to digital converter (ADC), which is directly commanded and controlled by the FPGA.

Polzin, Kurt A.↗

Automatic control of clock duty cycle

In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Feng, Xiaoxin↗

Coilgun Acceleration Model Containing Multiple Interacting Coils

A coilgun operates by pulsing current through an axially-arranged series of independently-controlled coils inductively interacting with a small, electrically-conductive, azimuthally-symmetric projectile to accelerate it to high velocities. The electrical circuits are programmed to pulse current through the coils in such a way so as to impart further electromagnetic acceleration in each stage. A method is developed to calculate the mutual inductance between the coils and between each coil and the projectile. These terms are used to write a system of first-order ordinary differential equations governing the projectile velocity and the current flow in each coil. While the inclusion of the electromagnetic interactions between coils significantly complicates the equation set as more coil sets are included in the problem, casting the problem symbolically in mass matrix form permits solution using standard numerical Runge-Kutta techniques. Comparing a projectile with a single-turn to that comprised of nine-turns, the inductance of the former is much smaller, but this leads to a greater induced projectile current. The lower inductance and greater current appear to offset each other with little difference in the acceleration profile for the two cases. For the limited cases studied, coils with a discharge half-cycle equal to the time for a projectile to transit from one coil to the next yield increased efficiency.

Polzin, Kurt A.↗

Method and apparatus for measuring frequency and phase difference

A system for deriving direct digital indications of frequency and phase difference between two incoming pulse trains adaptable for collision avoidance systems or the like. A pair of radar beams 152 and 152A are directed toward a target 153 and corresponding beams 154 and 154A returning therefrom are detected. A digital difference circuit 110 forms a pulse train 66 from the Doppler shift frequencies of each beam pair having a repetition rate functionally related to the difference in magnitude of the shift frequencies. Pulses from the pulse train are counted as a function of time. Visual indications thereof on display 144 are correlative to target position relative to beams 152 and 152A.

Kobayashi, Herbert S.↗

Pulse transducer with artifact signal attenuator

An artifact signal attenuator for a pulse rate sensor is described. The circuit for attenuating background noise signals is connected with a pulse rate transducer which has a light source and a detector for light reflected from blood vessels of a living body. The heart signal provided consists of a modulated dc signal voltage indicative of pulse rate. The artifact signal resulting from light reflected from the skin of the body comprises both a constant dc signal voltage and a modulated dc signal voltage. The amplitude of the artifact signal is greater and the frequency less than that of the heart signal. The signal attenuator circuit includes an operational amplifier for canceling the artifact signal from the output signal of the transducer and has the capability of meeting packaging requirements for wrist-watch-size packages.

Cash, W. H., Jr.↗

Programmable Pulser

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Baumann, Eric↗

External electro-optic probing of millimeter-wave integrated circuits

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.↗

External electro-optic probing of millimeter-wave integrated circuits

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.↗

5KW pulse width modulated static inverter

Design verification tests for logic and low level circuits, and preliminary single-phase breadboard of pulse width modulated static inverter

PULSE WIDTH MODULATION /PWM/↗

System and method for determining velocity of electrically conductive fluid

A flowing electrically-conductive fluid is controlled between an upstream and downstream location thereof to insure that a convection timescale of the flowing fluid is less than a thermal diffusion timescale of the flowing fluid. First and second nodes of a current-carrying circuit are coupled to the fluid at the upstream location. A current pulse is applied to the current-carrying circuit so that the current pulse travels through the flowing fluid to thereby generate a thermal feature therein at the upstream location. The thermal feature is convected to the downstream location where it is monitored to detect a peak associated with the thermal feature so-convected. The velocity of the fluid flow is determined using a time-of-flight analysis.

Polzin, Kurt A.↗

Wide Range SET Pulse Measurement

A method for measuring a wide range of SET pulses is demonstrated. Use of dynamic logic, faster than ordinary CMOS, allows capture of short pulses. A weighted binning of SET lengths allows measurement of a wide range of pulse lengths with compact circuitry. A pulse-length-conservative pulse combiner tree routes SETs from combinational logic to the measurement circuit, allowing SET measurements in circuits that cannot easily be arranged in long chains. The method is applied to add-multiplex combinational logic, and to an array of NFET routing switches, at .35 micron. Pulses are captured in a chain of Domino Logic AND gates. Propagation through the chain is frozen on the trailing edge by dropping low the second "enable" input to the AND gates. Capacitive loading is increased in the latter stages to create an approximately logarithmic weighted binning, so that a broad range of pulse lengths can be captured with a 10 stage capture chain. Simulations show pulses can be captured which are 1/5th the length of those typically captured with leading edge triggered latch methods, and less than the length of those captured with a trailing edge latch method. After capture, the pulse pattern is transferred to an SEU protected shift register for readout. 64 instances of each of two types of logic are used as targets. One is a full adder with a 4 to 1 mux on its inputs. The other is a 4 x 4 NFET routing matrix. The outputs are passed through buffered XNOR comparators to identify pulses, which are merged in a buffered not-nand (OR) tree designed to avoid pulse absorption as much as possible. The output from each of the two test circuits are input into separate pulse measurement circuits. Test inputs were provided so that the circuit could be bench tested and calibrated. A third SET measurement circuit with no inputs was used to judge the contribution from direct hits on the measurement circuit. Heavy ions were used with an LET range from 12 to 176. At LET of 21 and below, the very small number of SETs were not significantly higher in the test over the control circuits. At higher LET the test circuit SETs are one or two orders of magnitude greater than for the control circuit. The NFET circuit produces more and slightly longer SETs as expected. But the differences do not appear to be significant enough to modify strategies now used to avoid capture of SETs in chips such as FPGAs. Complete data and graphs will be in the full paper / presentation. In the summary figure below left, NOCL is the reference circuit without any input, and number of stages triggered is plotted. Simulation at right shows the smallest pulse captured (stage 2) at about 300 ps. Our conclusion is that the method is promising, but that improvements in the merge network are desirable before applying in a deep submicron process

Shuler, Robert L.↗