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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS2017

Ultra-Stable Segmented Telescope Sensing and Control Architecture

The LUVOIR team is conducting two full architecture studies. Architecture A - 15 meter telescope that folds up in an 8.4m SLS Block 2 shroud is nearly complete. Architecture B - 9.2 meter that uses an existing fairing size will begin study this Fall. This talk will summarize the ultra-stable architecture of the 15m segmented telescope including the basic requirements, the basic rationale for the architecture, the technologies employed, and the expected performance. This work builds on several dynamics and thermal studies performed for ATLAST segmented telescope configurations. The most important new element was an approach to actively control segments for segment to segment motions which will be discussed later.

Telescope↗

NASA NTRSDate not supplied

Layered Electrode Architectures Enabled by Holey Graphene Hosts

Battery electrodes are typically prepared using a slurry-based method, where high boiling point organic solvents are typically used with a polymer binder to disperse active electrode materials and conductive carbon additives followed by casting into current collector sheets. In this process, the use of organic solvents are environmentally hazardous, energy intensive, and time-consuming, while polymeric binders add weight and can undergo parasitic reactions during battery cycling. Here we discuss the use of a unique conductive carbon nanomaterial, namely holey graphene, as a multifunctional host that can be processed via a facile, solvent-free, binder-free, cold pressing method to prepare electrodes with unique architectures. This approach can accommodate a broad range of battery chemistries, such as lithium oxygen/carbon dioxide (Li-O2/CO2), lithium sulfur/selenium (Li-S/Se), and various lithium ion chemistries. The successful use of dry, cold compression allows the convenient modification of electrode mass loading with unique architectures containing active materials randomly mixed or layered with single or multiple layers of one or more active materials. In the conventional slurry-based electrode fabrication method, it is difficult, if not impossible, to achieve such layered architectures. In particular, the layered electrode architectures from the dry, cold press approach are easy to fabricate without significantly sacrificing device performance, and are amenable to continuous roll-to-roll dry processing. In addition, these architectures offer unprecedented perspectives on the battery material loading vs. utilization efficiency, as well as enabling unique characterization opportunities to advance mechanistic understanding of various battery chemistries. Potential applications of this unique electrode fabrication approach for solid-state batteries will also be discussed.

holey graphene, batteries, electrode architecture,↗

NASA NTRS1995

A Multi-Mission Space Avionics Architecture

As the budget for the space industry is dwindling, a reusable avionics architecture applicable across multiple missions is urgently needed to reduce the development and production costs of flight projects. This paper presents a multi-mission avionics architecture which employs interface standards extensively, sot hat avionics systems can be built rapidly by assembling subsystems and instruments in a plug-and-play manner. The key feature of this architecture is a "backbone" standard parallel bus which can accommodate various standard interfaces through a repertoire of I/O modules. Hence, specific ;mission requirements can be met by selecting and integrating the appropriate subsystems and instruments into the system. This architecture can also adopt different "backbone" buses, implement redundant processors, and support distributed processing. An example of the architecture using the MOPS6000 from the Southwest Research Institute is also described. Experiments will be done in the Flight System Testbed (FST) of the Jet Propulsion Laboratory to benchmark the MOPS6000 and to demonstrate its multi-mission capability.

Avionics↗

DOE OSTI2026

Two Artificial Leaf Architectures for Solar Formate Production From CO 2 and H 2 O

Sunlight-powered artificial leaves for the production of formate from CO 2 are an attractive route to solar fuels, yet existing solar formate devices remain low in performance, and their architecture and material choices are underexplored. Herein, we report the fabrication of two distinct fully integrated, self-standing solar formate device architectures and elucidate the underlying design principles and material selection strategies. The first architecture integrates a Si photocathode with a BiVO 4 photoanode and utilizes a highly active Pd catalyst for CO 2 reduction. It represents the first artificial leaf device comprising two photoelectrodes (excluding photovoltaic [PV]-biased electrodes) for effective formate production under single-beam illumination. The second architecture employs a dark cathode and a dark anode driven by a 4-junction perovskite solar cell and uses a highly stable Bi catalyst for CO 2 reduction. This device delivers a record-high formate production rate of 174 µmol h −1 with a remarkable solar-to-formate energy efficiency of 2% among all artificial leaf devices reported to date. Finally, these results demonstrate the feasibility and outline the design principles of both PV-free and PV-assisted device architectures in solar fuel production.

electrocatalysis↗

DOE OSTI2026

Holistic energy analysis method for thermal management architectures of data centers

Modern high-performance computing (HPC) data centers (DCs), particularly those supporting energy-intensive artificial intelligence (AI) workloads, face escalating thermal management challenges that degrade performance through thermal throttling and drive up cooling power consumption and operational costs. To address this challenge, many have developed a wide variety of thermal management solutions (single-phase, two-phase, direct, indirect, hybrid, and more) which attempt to cool HPC DCs effectively while attempting to minimize overall system power consumption. However, the analysis of these solutions and methods to effectively compare one with another is lacking. Overall power usage effectiveness (PUE) and total-power usage effectiveness (TUE) provide a metric to quantify power consumption but fail to identify components in the system which require further optimization. To address this, we propose a holistic analytical framework – the waterfall diagram (WFD) – which leverages a waterfall chart methodology, offering a comprehensive visualization of both the thermal management system loop and heat flow pathways from individual server components to the outdoor ambient. Use of the WFD enables graphical estimations of power efficiency and cooling performance across each component of a DC cooling system and complements Sankey-style energy flow visualizations by additionally resolving stage-wise temperature changes and incremental TUE contributions. The framework is used in conjunction with simulation-based approaches, to conduct a detailed pressure drop and flow distribution analysis aimed at identifying the optimal coolant distribution architecture for a single-phase direct-to-chip water-cooled DC, which serves as the baseline for subsequent WFD analysis. Among the evaluated architectures, the 3 U modular coolant distribution architecture is found to demonstrate the best performance, considering minimal pressure drop and uniform flow distribution. In addition, TUE is calculated for each cooling loop component based on its associated pressure drop and corresponding pumping power, which are integrated into the WFD. This correlation between TUE and local temperature offers immediate insight into the power efficiency and thermal performance contributions of individual components, facilitating further development and optimization. Examples of WFD applications are presented under varying thermal loads and ambient conditions, demonstrating reasonable cooling strategies. Notably, the 3 U modular architecture maintains a consistent chip case temperature of 85°C, achieving a TUE of 1.016 at ambient temperature of 47°C, and a TUE of 1.026 at ambient temperature of 52°C. The WFD methodology provides an efficient, holistic, and streamlined framework for DC thermal management architecture assessment and enables design optimization which is important for addressing the thermal-fluidic energy challenges of current and next-generation DCs.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗

DOE OSTI2025

From Edge to HPC: Investigating Cross-Facility Data Streaming Architectures

In this paper, we investigate three cross-facility data streaming architectures, Direct Streaming (DTS), Proxied Streaming (PRS), and Managed Service Streaming (MSS). We examine their architectural variations in data flow paths and deployment feasibility, and detail their implementation using the Data Streaming to HPC (DS2HPC) architectural framework and the SciStream memory-to-memory streaming toolkit on the production-grade Advanced Computing Ecosystem (ACE) infrastructure at Oak Ridge Leadership Computing Facility (OLCF). We present a workflow-specific evaluation of these architectures using three synthetic workloads derived from the streaming characteristics of scientific workflows. Through simulated experiments, we measure streaming throughput, round-trip time, and overhead under work sharing, work sharing with feedback, and broadcast and gather messaging patterns commonly found in AI-HPC communication motifs. Our study shows that DTS offers a minimal-hop path, resulting in higher throughput and lower latency, whereas MSS provides greater deployment feasibility and scalability across multiple users but incurs significant overhead. PRS lies in between, offering a scalable architecture whose performance matches DTS in most cases.

George, Anjus [ORNL] (ORCID:0000000179737061)↗

DOE OSTI2024

On a Simplified Approach to Achieve Parallel Performance and Portability Across CPU and GPU Architectures

This paper presents software advances to easily exploit computer architectures consisting of a multi-core CPU and CPU+GPU to accelerate diverse types of high-performance computing (HPC) applications using a single code implementation. The paper describes and demonstrates the performance of the open-source C++ matrix and array (MATAR) library that uniquely offers: (1) a straightforward syntax for programming productivity, (2) usable data structures for data-oriented programming (DOP) for performance, and (3) a simple interface to the open-source C++ Kokkos library for portability and memory management across CPUs and GPUs. The portability across architectures with a single code implementation is achieved by automatically switching between diverse fine-grained parallelism backends (e.g., CUDA, HIP, OpenMP, pthreads, etc.) at compile time. The MATAR library solves many longstanding challenges associated with easily writing software that can run in parallel on any computer architecture. This work benefits projects seeking to write new C++ codes while also addressing the challenges of quickly making existing Fortran codes performant and portable over modern computer architectures with minimal syntactical changes from Fortran to C++. We demonstrate the feasibility of readily writing new C++ codes and modernizing existing codes with MATAR to be performant, parallel, and portable across diverse computer architectures.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1987

On-board processing satellite network architecture and control study

The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures. Use of the following transmission architecture was considered: satellite switched TDMA; TDMA up, TDM down; scanning (hopping) beam TDMA; FDMA up, TDM down; satellite switched MF/TDMA; and switching Hub earth stations with double hop transmission. A candidate network architecture will be selected that: comprises multiple access subnetworks optimized for each user; interconnects the subnetworks by means of a baseband processor; and optimizes the marriage of interconnection and access techniques. An overall network control architecture will be provided that will serve the needs of the baseband and satellite switched RF interconnected subnetworks. The results of the studies shall be used to identify elements of network architecture and control that require the greatest degree of technology development to realize an operational system. This will be specified in terms of: requirements of the enabling technology; difference from the current available technology; and estimate of the development requirements needed to achieve an operational system. The results obtained for each of these tasks are presented.

Campanella, S. Joseph↗

NASA NTRS1987

The architecture of a video image processor for the space station

The architecture of a video image processor for space station applications is described. The architecture was derived from a study of the requirements of algorithms that are necessary to produce the desired functionality of many of these applications. Architectural options were selected based on a simulation of the execution of these algorithms on various architectural organizations. A great deal of emphasis was placed on the ability of the system to evolve and grow over the lifetime of the space station. The result is a hierarchical parallel architecture that is characterized by high level language programmability, modularity, extensibility and can meet the required performance goals.

Yalamanchili, S.↗

NASA NTRS1989

Parallel Architectures for Planetary Exploration Requirements (PAPER)

The Parallel Architectures for Planetary Exploration Requirements (PAPER) project is essentially research oriented towards technology insertion issues for NASA's unmanned planetary probes. It was initiated to complement and augment the long-term efforts for space exploration with particular reference to NASA/LaRC's (NASA Langley Research Center) research needs for planetary exploration missions of the mid and late 1990s. The requirements for space missions as given in the somewhat dated Advanced Information Processing Systems (AIPS) requirements document are contrasted with the new requirements from JPL/Caltech involving sensor data capture and scene analysis. It is shown that more stringent requirements have arisen as a result of technological advancements. Two possible architectures, the AIPS Proof of Concept (POC) configuration and the MAX Fault-tolerant dataflow multiprocessor, were evaluated. The main observation was that the AIPS design is biased towards fault tolerance and may not be an ideal architecture for planetary and deep space probes due to high cost and complexity. The MAX concepts appears to be a promising candidate, except that more detailed information is required. The feasibility for adding neural computation capability to this architecture needs to be studied. Key impact issues for architectural design of computing systems meant for planetary missions were also identified.

Cezzar, Ruknet↗

NASA NTRS1990

Architecture independent environment for developing engineering software on MIMD computers

Engineers are constantly faced with solving problems of increasing complexity and detail. Multiple Instruction stream Multiple Data stream (MIMD) computers have been developed to overcome the performance limitations of serial computers. The hardware architectures of MIMD computers vary considerably and are much more sophisticated than serial computers. Developing large scale software for a variety of MIMD computers is difficult and expensive. There is a need to provide tools that facilitate programming these machines. First, the issues that must be considered to develop those tools are examined. The two main areas of concern were architecture independence and data management. Architecture independent software facilitates software portability and improves the longevity and utility of the software product. It provides some form of insurance for the investment of time and effort that goes into developing the software. The management of data is a crucial aspect of solving large engineering problems. It must be considered in light of the new hardware organizations that are available. Second, the functional design and implementation of a software environment that facilitates developing architecture independent software for large engineering applications are described. The topics of discussion include: a description of the model that supports the development of architecture independent software; identifying and exploiting concurrency within the application program; data coherence; engineering data base and memory management.

Valimohamed, Karim A.↗

NASA NTRS1990

A CDMA architecture for a Ka-band Personal Access Satellite System

A Code Division Multiple Access (CDMA) architecture is currently being studied for use in a Ka-band Personal Access Satellite System (PASS). The complete architecture consisting of block diagrams of the user terminal, the supplier station, the network management center, and the satellite is described along with the access methods and frequency/time plans. The complexity of developing this system using the CDMA architecture is compared to that of a Frequency Division Multiple Access (FDMA) architecture. The inherent advantages and disadvantages of the two architectures are compared and their respective capacities are discussed.

Motamedi, Masoud↗

NASA NTRS1990

Advanced Information Processing System (AIPS)-based fault tolerant avionics architecture for launch vehicles

An avionics architecture for the advanced launch system (ALS) that uses validated hardware and software building blocks developed under the advanced information processing system program is presented. The AIPS for ALS architecture defined is preliminary, and reliability requirements can be met by the AIPS hardware and software building blocks that are built using the state-of-the-art technology available in the 1992-93 time frame. The level of detail in the architecture definition reflects the level of detail available in the ALS requirements. As the avionics requirements are refined, the architecture can also be refined and defined in greater detail with the help of analysis and simulation tools. A useful methodology is demonstrated for investigating the impact of the avionics suite to the recurring cost of the ALS. It is shown that allowing the vehicle to launch with selected detected failures can potentially reduce the recurring launch costs. A comparative analysis shows that validated fault-tolerant avionics built out of Class B parts can result in lower life-cycle-cost in comparison to simplex avionics built out of Class S parts or other redundant architectures.

Lala, Jaynarayan H.↗

NASA NTRS1991

Architecture and design of a 500-MHz gallium-arsenide processing element for a parallel supercomputer

The design of the processing element of GASP, a GaAs supercomputer with a 500-MHz instruction issue rate and 1-GHz subsystem clocks, is presented. The novel, functionally modular, block data flow architecture of GASP is described. The architecture and design of a GASP processing element is then presented. The processing element (PE) is implemented in a hybrid semiconductor module with 152 custom GaAs ICs of eight different types. The effects of the implementation technology on both the system-level architecture and the PE design are discussed. SPICE simulations indicate that parts of the PE are capable of being clocked at 1 GHz, while the rest of the PE uses a 500-MHz clock. The architecture utilizes data flow techniques at a program block level, which allows efficient execution of parallel programs while maintaining reasonably good performance on sequential programs. A simulation study of the architecture indicates that an instruction execution rate of over 30,000 MIPS can be attained with 65 PEs.

Fouts, Douglas J.↗

NASA NTRS1991

Mark 4A antenna control system data handling architecture study

A high-level review was conducted to provide an analysis of the existing architecture used to handle data and implement control algorithms for NASA's Deep Space Network (DSN) antennas and to make system-level recommendations for improving this architecture so that the DSN antennas can support the ever-tightening requirements of the next decade and beyond. It was found that the existing system is seriously overloaded, with processor utilization approaching 100 percent. A number of factors contribute to this overloading, including dated hardware, inefficient software, and a message-passing strategy that depends on serial connections between machines. At the same time, the system has shortcomings and idiosyncrasies that require extensive human intervention. A custom operating system kernel and an obscure programming language exacerbate the problems and should be modernized. A new architecture is presented that addresses these and other issues. Key features of the new architecture include a simplified message passing hierarchy that utilizes a high-speed local area network, redesign of particular processing function algorithms, consolidation of functions, and implementation of the architecture in modern hardware and software using mainstream computer languages and operating systems. The system would also allow incremental hardware improvements as better and faster hardware for such systems becomes available, and costs could potentially be low enough that redundancy would be provided economically. Such a system could support DSN requirements for the foreseeable future, though thorough consideration must be given to hard computational requirements, porting existing software functionality to the new system, and issues of fault tolerance and recovery.

Briggs, H. C.↗

NASA NTRS1992

Architecture options for the Manned Transportation Systems Study

The Manned Transpiration System (MTS) Study was undertaken to develop key data relative to the United States manned transportation system, and specifically, the next manned system we build. These data are being developed in the context of Earth-to-orbit architectures necessary to deliver all government payloads to low Earth orbit (LEO). Launch systems, transition between current and new systems, along with system functions (personnel and/or cargo to/from orbit) are presented. Several key considerations being debated today were used to aid our selection of Earth-to-orbit (ETO) architectures for evaluation. Other consideration s not being addressed in this initial effort that require additional study are identified Twenty-five launch systems were used to define a set of 18 architectures. These architectures are discussed in context with they key considerations being addressed in this study. Payload manufacturing ground rules are presented to provide an understanding of our approach in establishing flight rates from the MTS mission models. Furthermore, a discussion of manned system flight rates and relative personnel safety characteristics differences is presented. Comparative architecture results will not be available until May 1992.

M T Gaunce↗

NASA NTRS1993

Space Generic Open Avionics Architecture (SGOAA) reference model technical guide

This report presents a full description of the Space Generic Open Avionics Architecture (SGOAA). The SGOAA consists of a generic system architecture for the entities in spacecraft avionics, a generic processing architecture, and a six class model of interfaces in a hardware/software system. The purpose of the SGOAA is to provide an umbrella set of requirements for applying the generic architecture interface model to the design of specific avionics hardware/software systems. The SGOAA defines a generic set of system interface points to facilitate identification of critical interfaces and establishes the requirements for applying appropriate low level detailed implementation standards to those interface points. The generic core avionics system and processing architecture models provided herein are robustly tailorable to specific system applications and provide a platform upon which the interface model is to be applied.

Wray, Richard B.↗