SEARCH · Search NASA

Results for “latency”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 181 records · Page 10

All sources NASA NTRS DOE OSTI

NASA NTRS2009

Combined MODIS/AMSR-E SST Composites for Regional Weather Applications

Recent applications of a high resolution MODlS composite SST product have clearly shown the importance of developing high-resolution SST data sets for coastal applications and modeling. In general, coupling between the oceans and atmospheres has been closely linked to SST gradients and fronts, indicating a need for high resolution SSTs, specifically in the areas of large gradients associated with coastal regions. Thus an accurate determination of SST gradients has become critical for determining the appropriate air-sea coupling and the influence on ocean modeling. Recent research is focused on improving the accuracy and spatial coverage of the current operational MODIS SST composite product provided by the Short-term Prediction Research and Transition (SPORT) project and distributed to the community. GHRSST-PP MODlS data and microwave AMSR-E data are being combined to produce composite data sets for both the West Coast and East Coast of the United States, including the Gulf of Mexico. The use of 1 km MODIS data has explicit advantages over other SST products including its global coverage and high resolution. The AMSR-E data will reduce the latency of the composites. A strategy for utilizing the error characteristics contained in the GHRSST data has been developed. This strategy will include using the error characteristics directly to calculate weights in the SST composites, uncertainty maps based on the composite biases and RMS errors, and latency products calculated in the compositing process. Recent accomplishments include the development of an enhanced compositing approach based on the error-weighted combination of recent clear MODIS SST values, where the error contributions come from measurement error, potential cloud contamination, and data latency sources. Future plans call for the inclusion of AMSR-E SST values with appropriate weights based upon measurement accuracy, MODIS-AMSR-E SST bias, and latency.

Jedlovec, Gary↗

NASA NTRS2012

Desert RATS 2011: Near-Earth Asteroid Human Exploration Operations

The Desert Research and Technology Studies (D-RATS) 2011 field test involved the planning and execution of a series of exploration scenarios under operational conditions similar to those that would be expected during a human exploration mission to a near-Earth asteroid (NEA). The focus was on understanding the operations tempo during simulated NEA exploration and the implications of communications latency and limited data bandwidth. Anchoring technologies and sampling techniques were not evaluated due to the immaturity of those technologies and the inability to meaningfully test them at D-RATS. Reduced gravity analogs and simulations are being used to fully evaluate Multi-Mission Space Exploration Vehicle (MMSEV) and extravehicular (EVA) operations and interactions in near-weightlessness at a NEA as part of NASA s integrated analogs program. Hypotheses were tested by planning and performing a series of 1-day simulated exploration excursions comparing test conditions all of which involved a single Deep Space Habitat (DSH) and either zero, one, or two MMSEVs; three or four crewmembers; one of two different communications bandwidths; and a 100-second roundtrip communications latency between the field site and Houston. Excursions were executed at the Black Point Lava Flow test site with a Mission Control Center and Science Support Room at Johnson Space Center (JSC) being operated with 100-second roundtrip communication latency to the field. Crews were composed of astronauts and professional field geologists and teams of Mission Operations, Science, and Education & Public Outreach (EPO) experts also supported the mission simulations each day. Data were collected separately from the Crew, Mission Operations, Science, and EPO teams to assess the test conditions from multiple perspectives. For the operations tested, data indicates practically significant benefits may be realized by including at least one MMSEV and by including 4 versus 3 crewmembers in the NEA exploration architecture as measured by increased Scientific Data Quality, EVA Exploration Time, Capability Assessment Ratings, and Overall Acceptability ratings by Crew, Mission Operations, Science, and Education & Public Outreach teams. A combination of text and voice was used to effectively communicate over the 100-second roundtrip communications latency and increased communication bandwidth yielded a small but practically significant improvement in Overall Acceptability as rated by the Science team, although the impact of bandwidth on scientific strategic planning was not assessed. No effect of increased bandwidth was observed with respect to Crew, Mission Operations, or EPO team ratings of Overall Acceptability.

Abercromby, Andrew↗

NASA NTRS2013

Coarse-Grain Bandwidth Estimation Scheme for Large-Scale Network

A large-scale network that supports a large number of users can have an aggregate data rate of hundreds of Mbps at any time. High-fidelity simulation of a large-scale network might be too complicated and memory-intensive for typical commercial-off-the-shelf (COTS) tools. Unlike a large commercial wide-area-network (WAN) that shares diverse network resources among diverse users and has a complex topology that requires routing mechanism and flow control, the ground communication links of a space network operate under the assumption of a guaranteed dedicated bandwidth allocation between specific sparse endpoints in a star-like topology. This work solved the network design problem of estimating the bandwidths of a ground network architecture option that offer different service classes to meet the latency requirements of different user data types. In this work, a top-down analysis and simulation approach was created to size the bandwidths of a store-and-forward network for a given network topology, a mission traffic scenario, and a set of data types with different latency requirements. These techniques were used to estimate the WAN bandwidths of the ground links for different architecture options of the proposed Integrated Space Communication and Navigation (SCaN) Network. A new analytical approach, called the "leveling scheme," was developed to model the store-and-forward mechanism of the network data flow. The term "leveling" refers to the spreading of data across a longer time horizon without violating the corresponding latency requirement of the data type. Two versions of the leveling scheme were developed: 1. A straightforward version that simply spreads the data of each data type across the time horizon and doesn't take into account the interactions among data types within a pass, or between data types across overlapping passes at a network node, and is inherently sub-optimal. 2. Two-state Markov leveling scheme that takes into account the second order behavior of the store-and-forward mechanism, and the interactions among data types within a pass. The novelty of this approach lies in the modeling of the store-and-forward mechanism of each network node. The term store-and-forward refers to the data traffic regulation technique in which data is sent to an intermediate network node where they are temporarily stored and sent at a later time to the destination node or to another intermediate node. Store-and-forward can be applied to both space-based networks that have intermittent connectivity, and ground-based networks with deterministic connectivity. For groundbased networks, the store-and-forward mechanism is used to regulate the network data flow and link resource utilization such that the user data types can be delivered to their destination nodes without violating their respective latency requirements.

Cheung, Kar-Ming↗

NASA NTRS2013

Understanding the Effects of Spaceflight on Head-trunk Coordination during Walking and Obstacle Avoidance

Prolonged exposure to spaceflight conditions results in a battery of physiological changes, some of which contribute to sensorimotor and neurovestibular deficits. Upon return to Earth, functional performance changes are tested using the Functional Task Test (FTT), which includes an obstacle course to observe post‐flight balance and postural stability, specifically during turning. Aims: To quantify changes in movement strategies during turning events by observing the latency between head‐andtrunk coordinated movement. Hypothesis: It is hypothesized that subjects experiencing neurovestibular adaptations will exhibit head‐to‐trunk locking ('en bloc' movement) during turning, exhibited by a decrease in latency between head and trunk movement. Sample: FTT data samples were collected from Shuttle and ISS missions. Samples were analyzed three times pre exposure, immediately post‐exposure (0 or 1 day post) and 2‐to‐3 times during recovery from the microgravity environment. Methods: Two 3D inertial measurements units (XSens MTx) were attached to subjects, one on the head and one on the upper back. This study focused primarily on the yaw movements about the subject's center of rotation. Time differences (latency) between head and trunk movement were calculated at two points: the first turn (Fturn) to enter the obstacle course (approximately 90⁰ turn) and averaged across a slalom obstacle portion, consisting of three turns (approximately three 90⁰ turns). Results: Preliminary analysis of the data shows a trend toward decreasing head‐to‐trunk movement latency during post‐flight ambulation, after reintroduction to Earth gravity in Shuttle and ISS astronauts. Conclusion: It is clear that changes in movement strategies are adopted during exposure to the microgravity environment and upon reintroduction to a gravity environment. Some subjects exhibit symptoms of neurovestibular neuropathy ('en bloc movement') that may impact their ability to perform post‐flight functional tasks.

Madansingh, S.↗

NASA NTRS2014

Understanding the Effects of Spaceflight on Head-trunk Coordination during Walking and Obstacle Avoidance

Prolonged exposure to spaceflight conditions results in a battery of physiological changes, some of which contribute to sensorimotor and neurovestibular deficits. Upon return to Earth, functional performance changes are tested using the Functional Task Test (FTT), which includes an obstacle course to observe post‐flight balance and postural stability, specifically during turning. The goal of this study was to quantify changes in movement strategies during turning events by observing the latency between head‐and‐trunk coordinated movements. It was hypothesized that subjects experiencing neurovestibular adaptations would exhibit head‐to‐trunk locking ('en bloc' movement) during turning, exhibited by a decrease in latency between head and trunk movement. FTT data samples were collected from ISS missions. Samples were analyzed three times pre‐exposure, immediately postexposure (1 day post) and 2‐to‐3 times during recovery from the microgravity environment. Two 3D inertial measurements units (XSens MTx) were attached to subjects, one on the head and one on the upper back. This study focused primarily on the yaw movements about the subject's center of rotation. Time differences (latency) between head and trunk movement were calculated at two points on the obstacle course: the first turn to enter the obstacle course (approximately 90⁰ turn) and averaged across a slalom obstacle portion, consisting of three turns (approximately three 90⁰ turns). Preliminary analysis of the data shows a trend toward decreasing head‐to‐trunk movement latency during postflight ambulation in slalom turning after reintroduction to Earth gravity in ISS astronauts. It is clear that changes in movement strategies are adopted during exposure to the microgravity environment and upon reintroduction to a gravity environment. Most ISS subjects exhibit symptoms of neurovestibular changes ('en bloc head and trunk movement) which may impact their ability to perform post‐flight functional tasks.

Madansingh, S.↗

NASA NTRS2014

Understanding the Effects of Spaceflight on Head-trunk Coordination During Walking and Obstacle Avoidance

Prolonged exposure to spaceflight conditions results in a battery of physiological changes, some of which contribute to sensorimotor and neurovestibular deficits. Upon return to Earth, functional performance changes are tested using the Functional Task Test (FTT), which includes an obstacle course to observe post-flight balance and postural stability, specifically during turning. The goal of this study was to quantify changes in movement strategies during turning events by observing the latency between head-and-trunk coordinated movements. It was hypothesized that subjects experiencing neurovestibular adaptations would exhibit head-to-trunk locking ('en bloc' movement) during turning, exhibited by a decrease in latency between head and trunk movement. FTT data samples were collected from 13 ISS astronauts and 26 male 70-day head down tilt bed rest subjects, including bed rest controls (10 BRC) and bed rest exercisers (16 BRE). Samples were analyzed three times pre-exposure, immediately post-exposure (0 or 1 day post) and 2-to-3 times during recovery from the unloading environment. Two 3D inertial measurements units (XSens MTx) were attached to subjects, one on the head and one on the upper back. This study focused primarily on the yaw movements about the subject's center of rotation. Time differences (latency) between head and trunk movement were averaged across a slalom obstacle portion, consisting of three turns (approximately three 60⁰ turns). All participants were grouped as 'decreaser' or 'increaser,' relating to their change in head-to-trunk movement latency between pre- and post- environmental adaptation measures. Space flight unloading (ISS) showed a bimodal response between the 'increaser' and 'decreaser' group, while both bed rest control (BRC) and bed rest exercise (BRE) populations showed increased preference towards a 'decreaser' categorization, displaying greater head-trunk locking. It is clear that changes in movement strategies are adopted during exposure to an unloading environment. These results further the understanding of vestibular-somatosensory convergence and support the use of bed rest as an exclusionary model to better understand sensorimotor changes in space flight.

Madansingh, S.↗

NASA NTRS2015

Measured Response for UAS Integration into the National Airspace System

The measured response (MR) is the response time of aircraft to Air Traffic Controller (ATCo) commands and clearances. The overall MR can be broken up into several components, including the pilot verbal latencies (MR1), the time between the end of an ATCo clearance and the beginning of the pilots read back, and the execution initiation latency (MR2), the time between the end of the ATCos clearance and when the pilot begins to execute a maneuver. The MR is a crucial concern for the integration of Unmanned Aircraft Systems (UAS) into the National Airspace System (NAS) due to potentially greater latencies stemming from remote pilot communication and command execution. As a result, it is important to quantify what latencies in verbal responding and command execution are acceptable for safe and efficient operations in the NAS. The present studies begin to address these issues in a series of four simulations supported by the UAS Integration into the NAS program.

UAS in the NAS↗

NASA NTRSDate not supplied

Zero-Trust Architecture for Autonomous Edge Computing

We are at the apex of an aviation revolution where autonomy will play a central role in enabling complex, multi-agent systems to communicate, interact, and collaborate on a myriad of applications spanning autonomous swarms to wild-fire management. Autonomy is not an absolute but rather a spectrum ranging from a system requiring significant human intervention to one requiring little to none [1]. For example, the extreme, in the case of an autonomous aircraft, is one that operates independently in the airspace interacting with all other elements (air traffic controllers, other pilots) as if it were a human pilot. Critical to this vision is an architecture that enables autonomous agents to interact with minimal latency. Edge computing is an emerging architecture where compute and storage is pushed to the ‘edge’ of the network in order to minimize the round-trip time from agent to resource thereby mitigating the latency associated with cloud-only based approaches. Additionally, services can generate massive amounts of data (e.g., video feeds), which may require analysis in near real-time. Moving this data to the cloud for further processing may not be feasible due to latency, bandwidth, and cost. Privacy, security, and reliability can also be improved by edge computing architectures. However, this geo-distributed and dynamic* architecture complicates the establishment of unambiguous network security boundaries and can lead to vulnerabilities including man in the middle attacks, replay attacks, physical security breaches of edge nodes, signal interception, etc. This motivates the need for zero-trust architectures [2–4] which de-emphasize the notion of static network perimeters and, as the name implies, do not instill any innate trust in any particular agent. It is required that all agents must be authorized and approved in every transaction. In this paper, we present a zero-trust architecture suitable for edge-computing applications that demand significant low-latency, security, privacy, and reliability.

zero trust↗

DOE OSTI2025

LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout

Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recently emerged as a promising solution to improve readout accuracy . Prior hardware implementations of DNN-based readout are resource-intensive and suffer from high inference latency, limiting their practical use in low-latency decoding and quantum error correction (QEC) loops. This paper proposes LUNA, a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95x reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art. LUNA enables scalable, low-footprint, and high-speed qubit readout, supporting the development of larger and more reliable quantum computing systems.

Farooq, M. A. [Arizona State U., Tempe]↗

DOE OSTI2024

Accelerating data acquisition with FPGA-based edge machine learning: a case study with LCLS-II

New scientific experiments and instruments generate vast amounts of data that need to be transferred for storage or further processing, often overwhelming traditional systems. Edge machine learning (EdgeML) addresses this challenge by integrating machine learning (ML) algorithms with edge computing, enabling real-time data processing directly at the point of data generation. EdgeML is particularly beneficial for environments where immediate decisions are required, or where bandwidth and storage are limited. In this paper, we demonstrate a high-speed configurable ML model in a fully customizable EdgeML system using a field programmable gate array (FPGA). Our demonstration focuses on an angular array of electron spectrometers, referred to as the ‘CookieBox,’ developed for the Linac Coherent Light Source II project. The EdgeML system captures 51.2 Gbps from a 6.4 GS s −1 analog to digital converter and is designed to integrate data pre-processing and ML inside an FPGA. Our implementation achieves an inference latency of 0.2 µs for the ML model, and a total latency of 0.4 µs for the complete EdgeML system, which includes pre-processing, data transmission, digitization, and ML inference. The modular design of the system allows it to be adapted for other instrumentation applications requiring low-latency data processing.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2026

ML–Enabled FPGA Framework for Fast Quantum State Discrimination in Mid-Circuit Measurement Regimes

Accurate and low-latency quantum state discrimination is essential for protocols involving mid-circuit measurement (MCM) and conditional feed-forward. In superconducting quantum systems, conventional readout pipelines transfer measurement data to host processors for post-processing, introducing millisecond-scale delays that far exceed qubit coherence times. To overcome this bottleneck, we present an in-situ machine learning (ML) inference engine implemented on an FPGA for real-time quantum state discrimination. Our design performs inference directly on digitized readout signals with 40 ns latency, supports both qubit and qutrit readout, and enables conditional operations without host-side intervention. This capability is critical for MCM and for feedback-driven protocols such as quantum error correction. We validate the system on superconducting transmon hardware, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. We further demonstrate conditional qutrit logic driven by FPGA-resident classification, highlighting the potential of low-latency ML-on-FPGA control for NISQ applications and scalable fault-tolerant quantum computing.

Vora, Neel [Lawrence Berkeley National Laboratory ↗

DOE OSTI2026

FLYING SERVING: On-the-Fly Parallelism Switching for Large Language Model Serving

Production LLM serving must simultaneously deliver high throughput, low latency, and sufficient context capacity under non-stationary traffic and mixed request requirements. Data parallelism (DP) maximizes throughput by running independent replicas, while tensor parallelism (TP) reduces per-request latency and pools memory for long-context inference. However, existing serving stacks typically commit to a static parallelism configuration at deployment; adapting to bursts, priorities, or long-context requests is often disruptive and slow. We present Flying Serving, a vLLM-based system that enables online DP-TP switching without restarting engine workers. Flying Serving makes reconfiguration practical by virtualizing the state that would otherwise force data movement: (i) a zero-copy Model Weights Manager that exposes TP shard views on demand, (ii) a KV Cache Adaptor that preserves request KV state across DP/TP layouts, (iii) an eagerly initialized Communicator Pool to amortize collective setup, and (iv) a deadlock-free scheduler that coordinates safe transitions under execution skew. Across three popular LLMs and realistic serving scenarios, Flying Serving improves performance by up to 4.79 × under high load and 3.47 × under low load while supporting latency- and memory-driven requests.

Gao, Shouwei [ORNL]↗

DOE OSTI2025

Even Higher-Level Synthesis: An Exploration of AI Hardware Accelerators using HLS4ML

With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.

Di Guglielmo, Giuseppe [Fermilab]↗

DOE OSTI2026

Intelligent Experiments through Real-Time AI: Fast Data Processing and Autonomous Detector Control for High-Energy Nuclear Experiments

The aim of this project is to develop software and hardware for fast real-time data processing and autonomous detector control and calibration for the sPHENIX and the future EIC experiments. Below summarizes Georgia Tech team efforts in the past year: 1. We developed a real-time clustering algorithm and FPGA-based pipeline architecture for processing fired pixel data from ALPIDE sensors in sPHENIX experiments. Our Columnar Clustering Co-Design introduces a hardware-aware, stream-friendly approach that segments pixel data by column pairs using a Column Pair Clustering (CPC) strategy, followed by Cluster Stitching to merge adjacent subclusters. Implemented in Vitis HLS, the pipeline comprises five stages—read-in, subclustering, stitching, analysis, and write-out—connected by tagged HLS streams with custom end-of-event signaling for robust synchronization. We designed a pipelined dataflow model optimized for throughput, low latency, and minimal buffering, enabling scalable clustering across events of arbitrary size. Our system maintains spatial precision via center-of-mass and shape key extraction and efficiently handles edge cases such as fragmented or nested clusters. Compared against DBSCAN in both software and hardware, our approach demonstrates competitive performance under FPGA constraints. 2. We also conducted a comprehensive algorithm-to-hardware co-design of connected component analysis tailored for sPHENIX experiments, focusing on real-time, low-latency processing using FPGAs and High-Level Synthesis (HLS). Starting from a Python-based particle tracking pipeline, the team translated the core logic—graph traversal via DFS and Union-Find—into an HLS-compatible C++ model, replacing dynamic memory and recursion with static arrays and pipelined control flow. The final design includes a fully streamed and dataflow-compatible Union-Find kernel optimized across five iterations, incorporating loop pipelining, array partitioning, AXI/FIFO interface tuning, and function flattening. Experimental results show up to 14.8× speedup over the CPU baseline, reducing per-graph latency to 1.58 μs and demonstrating strong resource efficiency with only ~7k LUTs and zero BRAM usage. The design maintains functional correctness against the Python reference using a Python-based C-simulation framework and Mean Squared Error metrics. This work validates the potential of HLS-driven FPGA designs for edge-level HEP data acquisition, laying a scalable foundation for future integration with real-time detector pipelines and multi-graph processing systems.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

DOE OSTI2026

CMS Storage Performance with RNTuple

CMS is transitioning to use ROOT’s new RNTuple data storage format for the files CMS will write in the HL-LHC era. Based on initial tests, CMS expects faster I/O and smaller files compared to the present TTree storage format. This contribution will show a comprehensive performance comparison between RNTuple and TTree I/O using CMS AOD and MiniAOD data formats as test cases for both simulation and collision data corresponding to similar data taking conditions of LHC Run 3. Quantities such as the resulting file size, the memory usage of the I/O components, and the rate of events being read from a file or written to a file will be measured. CMS’ data processing relies heavily on reading files over the local or wide area networks. The file read patterns are important because the latencies have been seen to influence the total production job times. Therefore a study on the file read patterns will be conducted by recording traces of the offset, size, and timestamp of each read request for both RNTuple and TTree. The behavior of network reads will be mimicked by reading local files where artificial latency will be added to the read requests. The effect of different latency values on the job times will be studied.

Jones, Christopher D. [Fermilab]↗

DOE OSTI2026

Real-Time Inference For MI/RR Deblending

The Fermilab Main Injector (MI) and Recycler Ring (RR) share a common beam loss monitor (BLM) system, making loss events difficult to attribute to their source machine when beam is present in both simultaneously. The Real-time Edge AI for Distributed Systems (READS) project addresses this by deblending BLM readings in real time using machine learning (ML). The current FPGA based implementation meets the sub-3 ms latency requirement but carries a resource intensive hls4ml development cycle, motivating exploration of GPU based deployment. This paper characterizes inference latency on an NVIDIA Jetson Orin Nano and introduces a packet organization scheme for assembling synchronized event frames from seven distributed BLM DAQ streams. Using a Python based DAQ simulation with injected timing jitter in place of unavailable live beam data, the pipeline achieved an average end to end latency of 0.456 ms (σ = 0.122 ms) across 167,000 test frames, comfortably meeting the timing constraint. Early outliers were attributed to TensorRT warm-up rather than steady state limitations, suggesting GPU based inference is a viable alternative to the existing FPGA implementation.

Yu, Kellen [Cornell U.]↗

DOE OSTI2026

SuperLab 2.0 Showcase: Connecting Five Labs to Tackle Grid Complexity and Unlock Unique Grid Asset Potential

SuperLab 2.0 (5-Lab Demo) is a collaborative, national-scale experiment showcasing the coordination of geographically distributed energy assets in real time. The demonstration integrates 25 physical and digital assets, spanning wind, PV, batteries, electrolyzers, DC fast chargers, microgrid controllers, building automation systems, small modular reactor (SMR), control centers, and gas turbines, across five DOE national laboratories-NLR, INL, NETL, LBNL, and SNL. These assets are unified using Energy Sciences Network (ESnet), a low-latency, high-performance U.S. Department of Energy's (DOE) network, and controlled via a centralized energy controller hosted at NLR's ARIES facility. The demonstration validates the ability to stress-test hybrid energy systems under dynamic scenarios to de-risk advanced control strategies for greater resilience and flexibility. SuperLab 2.0 (5-Lab Demo) showcased a major advancement in federated national laboratory collaboration, enabling real-time, cross-laboratory experimentation to coordinate geographically dispersed distributed energy resources (DERs) using various communication protocols and networks. SuperLab 2.0 (5-Lab Demo) built on previous demonstrations conducted between NLR-PNNL and NLR-INL connecting diverse assets including distant protection devices, a SMR simulator, and a high temperature electrolyzer (HTE). Previous demos were based on a single connection between two labs with minimal coordination challenges. The 5-Lab demo with a centralized controller, distributed testbeds across different geographical locations, and use of protocols-based communication represents a scenario closer to real-world grid operations that coordinate resources across a region to meet system needs. This experiment studied how local DER controllers interact with a centralized energy controller during normal and abnormal events to maintain reliability. The SuperLab team across the five labs implemented a notional power system model equivalent of transmission and distribution lines, represented by the data networks interconnecting the labs. Each lab continuously exchanged local parameters (such as P and Q) from its Hardware-In-Loop (CHIL) and Power Hardware-In-Loop (PHIL) assets through centralized energy controller at NLR, enabling real-time interaction and coordination across sites. By leveraging ESnet as the communication backbone, the team successfully operated the distributed assets as a unified power system, with each bus represented by a different laboratory. This setup mirrors how assets interact in real-world power systems across dispersed locations with various protocols and latencies. At each lab site, assets were operated using their own local controllers which were coordinated through an overarching operation and control layer of centralized energy controller, equivalent to how an energy management system (EMS) orchestrates assets across a regional or national grid. SuperLab's federated connectivity utilized a Digital Real-Time Simulators (DRTS)-type gateway to connect Controller Hardware-In-Loop (CHIL) and PHIL assets between labs. To enable this federated connection through ESnet, a deterministic network was established where latency variations were consistent. This consistency allowed the development of digital filters for the power system assets across CHIL and PHIL interfaces to avoid unstable and unreliable grid conditions. This report provides an overview of the cross-laboratory configuration and offers insights into interconnecting geographically distributed research assets to test them as if they were co-located. This experiment represents a step toward linking nine DOE national laboratories, enabling nation-wide simulations that can address utility-driven challenges with grid resilience, flexibility, and modernization.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS1975

Brainstem auditory evoked responses in man. 1: Effect of stimulus rise-fall time and duration

Short latency (under 10 msec) responses elicited by bursts of white noise were recorded from the scalps of human subjects. Response alterations produced by changes in the noise burst duration (on-time), inter-burst interval (off-time), and onset and offset shapes were analyzed. The latency of the most prominent response component, wave V, was markedly delayed with increases in stimulus rise time but was unaffected by changes in fall time. Increases in stimulus duration, and therefore in loudness, resulted in a systematic increase in latency. This was probably due to response recovery processes, since the effect was eliminated with increases in stimulus off-time. The amplitude of wave V was insensitive to changes in signal rise and fall times, while increasing signal on-time produced smaller amplitude responses only for sufficiently short off-times. It was concluded that wave V of the human auditory brainstem evoked response is solely an onset response.

Hecox, K.↗