High Speed CMOS Binary Active Pixel Image Sensor
A highly integrated active pixel sensor with on-chip 1 bit thresholding circuitry achieving an 8,000.
CMOS Image Sensor↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology
A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.
Space Microelectronics Image Sensors APS Digital I↗
CMOS Image Sensors: Electronic Camera On A Chip
Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.
Space Microelectronics Image Sensors APS Digital I↗
Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology
A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.
Space Microelectronics Image Sensors APS Digital I↗
Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications
JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.
solid-state image sensors active pixel sensor APS ↗
Active Pixel Sensors: Are CCD's Dinosaurs?
Charge-coupled devices (CCD's) are presently the technology of choice for most imaging applications. In the 23 years since their invention in 1970, they have evolved to a sophisticated level of performance. However, as with all technologies, we can be certain that they will be supplanted someday. In this paper, the Active Pixel Sensor (APS) technology is explored as a possible successor to the CCD. An active pixel is defined as a detector array technology that has at least one active transistor within the pixel unit cell. The APS eliminates the need for nearly perfect charge transfer -- the Achilles' heel of CCDs. This perfect charge transfer makes CCD's radiation 'soft,' difficult to use under low light conditions, difficult to manufacture in large array sizes, difficult to integrate with on-chip electronics, difficult to use at low temperatures, difficult to use at high frame rates, and difficult to manufacture in non-silicon materials that extend wavelength response.
Fossum, Eric R.↗
A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems
A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.
Mendis, Sunetra K.↗
Rapid evolution of analog circuits configured on a field programmable transistor array
The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.
SABLES analog circuits field programmable transist↗
Fault detection and bypass in a sequence information signal processor
The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.
Peterson, John C.↗
Bubble domain circuit organization
An on-chip bubble domain circuit organization. One or more storage registers are connected to a propagation path whereby data in the form of magnetic bubble domains (bubbles) may be transferred into and out of the storage registers. The propagation path includes a generator for producing the initial bubbles which are expanded into any desired number of new bubbles by a unique multiple output replicator. A unique input decoder is utilized to determine to which storage register the bubbles from the replicator will be directed along the propagation path. Those bubbles not selected may be annihilated. An output decoder utilizing essentially the same decoding scheme as the input decoder, selectively receives bubbles from the storage register. A transfer and replicate switch is utilized between the storage register and output decoder to selectively transfer bubbles to the output decoder. The output decoder may collapse all of the bubbles from certain storage registers so that only the information from the selected storage register reaches the detector. The detectors in turn produce the chip output signal. External control electronics are utilized to control the selective operation of the various devices utilized in the propagation path.
Chen, Thomas T.↗
Application of New Technology to Future Celestial Trackers
New developments in image sensors and optical materials have opened the door to dramatic mass and power reductions in celestial tracker designs. The rapid development of active pixel sensors (APS) has provided a new detector choice offering high on-chip integration of support circuitry at reduced power consumption. Silicon-Carbide (Si-C) optics are one of the new developments in low-mass optical components. We describe the celestial tracker needs of an Autonomous Feature and Star Tracking (AFAST) system designed for autonomous spacecraft control. Details of a low mass celestial tracker, based on a low power APS array and optimized for an AFAST system, are discussed.
active↗
Programmable Multiresolution CMOS Active Pixel Sensor
CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The resolution frame rate is 30 Hz with higher rates for all other image resolutions.
APS↗
Application of the Active Pixel Sensor Concept to Guidance and Navigation
Charge-coupled devices (CCDs) have been used extensively in the past in star trackers and fine guidance systems. A new technology, the active pixel sensor, is a possible successor to CCDs. This technology potentially features the same sensitivity and performance of the CCD with additional improvements. These improvements include random access capability, easy window-of-interest readout, non-destructive readout for signal-to-noise improvement, high radiation tolerance, simplified clocking voltages, and easy integration with other on-chip signal processing circuitry. The state-of-the-art of this emerging technology and its potential application to guidance and navigation systems is discussed.
Eisenman, Allan R.↗
256X256 CMOS Active Pixel Sensor Camera-on-a-Chip
A CMOS imaging sensor is described that uses active pixel sensor (APS) technology which permits the integration of the detector array with on-chip timing, control and signal chain electronics. This sensor has been used to implement a CMOS APS camera-on-a-chip.
active↗
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.
Limaye, Ankur M. (ORCID:0000000194062584)↗
Design and Performance of the SPT-SLIM Receiver Cryostat
The South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM) is a millimeter-wavelength line-intensity mapping experiment, which was deployed on the South Pole Telescope (SPT) during the 2024-2025 Austral summer season. This pathfinder experiment serves to demonstrate the on-sky operation of multi-pixel on-chip spectrometer technology. We report on the cryogenic performance of the SPT-SLIM receiver for the first year of commissioning observations. The SPT-SLIM receiver utilizes an Adiabatic Demagnetization Refrigerator (ADR) for cooling the focal plane of superconducting filterbank spectrometers to a temperature of 150 mK. We demonstrate stable thermal performance of the focal plane module during observations consistent with thermal modeling, enabling a cryogenic operating efficiency above 80%. We also report on the receiver control system design utilizing the Observatory Control System (OCS) platform for automated cryogenic operation on the SPT.
Young, M. R. [Fermilab; Chicago U., KICP]↗
An On-Sky Atmospheric Calibration of SPT-SLIM
We present the methodology and results of the on-sky responsivity calibration of the South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM). SPT-SLIM is a pathfinder line intensity mapping experiment utilizing the on-chip spectrometer technology, and was first deployed during the 2024-2025 Austral Summer season on the South Pole Telescope. During the two-week on-sky operation of SPT-SLIM, we performed periodic measurements of the detector response as a function of the telescope elevation angle. Combining these data with atmospheric opacity measurements from an on-site atmospheric tipping radiometer, simulated South Pole atmospheric spectra, and measured detector spectral responses, we construct estimates for the responsivity of SPT-SLIM detectors to sky loading. We then use this model to calibrate observations of the moon taken by SPT-SLIM, cross-checking the result against the known brightness temperature of the Moon as a function of its phase.
Dibert, K. R. [Chicago U., Astron. Astrophys. Ctr.↗
Obsidian
Obsidian A35 is a compact FPGA carrier board designed to interface with ADCs, DACs or other devices, either stand-alone or as an I/O expansion board. The connectivity includes 1 GigE, 4 SFP, 6 PMOD, FTDI USB and Arduino shield compatible header. The board features also a FPGA boot SPI Flash, on-chip DDR3 memory, VCXO and White Rabbit compatibility.
Moore, Victoria [Lawrence Berkeley National Labora↗