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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS2015

Cosmology Large Angular Scale Surveyor (CLASS) Focal Plane Development

The Cosmology Large Angular Scale Surveyor (CLASS) will measure the polarization of the Cosmic Microwave Background to search for and characterize the polarized signature of inflation. CLASS will operate from the Atacama Desert and observe approx.70% of the sky. A variable-delay polarization modulator provides modulation of the polarization at approx.10Hz to suppress the 1/f noise of the atmosphere and enable the measurement of the large angular scale polarization modes. The measurement of the inflationary signal across angular scales that spans both the recombination and reionization features allows a test of the predicted shape of the polarized angular power spectra in addition to a measurement of the energy scale of inflation. CLASS is an array of telescopes covering frequencies of 38, 93, 148, and 217 GHz. These frequencies straddle the foreground minimum and thus allow the extraction of foregrounds from the primordial signal. Each focal plane contains feedhorn-coupled transition-edge sensors that simultaneously detect two orthogonal linear polarizations. The use of single-crystal silicon as the dielectric for the on-chip transmission lines enables both high efficiency and uniformity in fabrication. Integrated band definition has been implemented that both controls the bandpass of the single-mode transmission on the chip and prevents stray light from coupling to the detectors.

polarized signature of inflation↗
NASA NTRS2016

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

Body of Knowledge (BOK)↗
NASA NTRS2016

A Cryogenic Waveguide Mount for Microstrip Circuit and Material Characterization

A waveguide split-block fixture used in the characterization of thin-film superconducting planar circuitry at millimeter wavelengths is described in detail. The test fixture is realized from a pair of mode converters, which transition from rectangular-waveguide to on-chip microstrip-line signal propagation via a stepped ridge-guide impedance transformer. The observed performance of the W-band package at 4.2K has a maximum in-band transmission ripple of 2dB between 1.53 and 1.89 times the waveguide cutoff frequency. This metrology approach enables the characterization of superconducting microstrip test structures as a function temperature and frequency. The limitations of the method are discussed and representative data for superconducting Nb and NbTiN thin film microstrip resonators on single-crystal Si dielectric substrates are presented.

U-yen, Kongpop↗
NASA NTRS2016

A Cryogenic Waveguide Mount for Microstrip Circuit and Material Characterization

A waveguide split-block fixture used in the characterization of thin-film superconducting planar circuitry at millimeter wavelengths is described in detail. The test fixture is realized from a pair of mode converters, which transition from rectangular-waveguide to on-chip microstrip-line signal propagation via a stepped ridge-guide impedance transformer. The observed performance of the W-band package at 4.2K has a maximum in-band transmission ripple of 2dB between 1.53 and 1.89 times the waveguide cutoff frequency. This metrology approach enables the characterization of superconducting microstrip test structures as a function temperature and frequency. The limitations of the method are discussed and representative data for superconducting Nb and NbTiN thin film microstrip resonators on single-crystal Si dielectric substrates are presented.

U-yen, Kongpop↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRSDate not supplied

NASA’s Orbital Debris Optical Program: ES-MCAT Nearing Full Operational Capability (FOC)

The NASA JAO/ES-MCAT (Eugene Stansbery Meter Class Autonomous Telescope) Facility is nearing Full Operational Capability, or FOC. ES-MCAT is now fully capable of autonomously running all observations, including: (a) monitoring weather and closing when conditions are not safe, as well as halting observations when conditions are not suitable (e.g. too cloudy) for operations, (b) start-up/shut-down nightly tasking, (c) collecting calibration data and survey or TLE-tracked data, and (d) processing all collected data, including on-chip photometry and astrometry calibrations using the GAIA star catalogue. The processed data are then further analyzed at NASA Johnson Space Center to correlate detections with known objects in the Space Surveillance Network (SSN) catalogue. MCAT can collect data of specific objects with known orbits or can search for objects with orbits similar to those of spacecraft or rocket bodies that have recently broken up. However, the primary goal for ES-MCAT is to survey the geosynchronous (GEO) belt to provide a statistical sample of the GEO debris environment for both engineering models for spacecraft designers and long-term environment evolutionary purposes. The approach for sweeping the sky to statistically survey GEO has been investigated and updated from past surveys taken by NASA and will be reported, herein referred to as the Candy Cane method. ES-MCAT’s optical performance and the limiting magnitude for the full optical system will be discussed. An analysis used to determine which filter to use for GEO surveys (SDSS r′) includes combining the reflectivity of the primary and secondary mirrors, transmission of the field corrector and CCD window, and the quantum efficiency of the CCD detector, resulting in throughput of the full optical path. This throughput is then combined with the expected typical transparency of the atmosphere at ES-MCAT’s altitude/location for the Sloan Digital Sky Survey (SDSS) g′r′i′z′ and Johnson/Kron-Cousins BVRI filters to yield expected relative throughput.

S. M. Lederer↗
NASA NTRS1995

Application of New Technology to Future Celestial Trackers

New developments in image sensors and optical materials have opened the door to dramatic mass and power reductions in celestial tracker designs. The rapid development of active pixel sensors (APS) has provided a new detector choice offering high on-chip integration of support circuitry at reduced power consumption. Silicon-Carbide (Si-C) optics are one of the new developments in low-mass optical components. We describe the celestial tracker needs of an Autonomous Feature and Star Tracking (AFAST) system designed for autonomous spacecraft control. Details of a low mass celestial tracker, based on a low power APS array and optimized for an AFAST system, are discussed.

active↗
NASA NTRS1996

Programmable Multiresolution CMOS Active Pixel Sensor

CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The resolution frame rate is 30 Hz with higher rates for all other image resolutions.

APS↗
NASA NTRS1993

Application of the Active Pixel Sensor Concept to Guidance and Navigation

Charge-coupled devices (CCDs) have been used extensively in the past in star trackers and fine guidance systems. A new technology, the active pixel sensor, is a possible successor to CCDs. This technology potentially features the same sensitivity and performance of the CCD with additional improvements. These improvements include random access capability, easy window-of-interest readout, non-destructive readout for signal-to-noise improvement, high radiation tolerance, simplified clocking voltages, and easy integration with other on-chip signal processing circuitry. The state-of-the-art of this emerging technology and its potential application to guidance and navigation systems is discussed.

Eisenman, Allan R.↗
NASA NTRS1996

256X256 CMOS Active Pixel Sensor Camera-on-a-Chip

A CMOS imaging sensor is described that uses active pixel sensor (APS) technology which permits the integration of the detector array with on-chip timing, control and signal chain electronics. This sensor has been used to implement a CMOS APS camera-on-a-chip.

active↗
NASA NTRS2012

Design and Operation of the Planetary In-Situ Capillary Electrophoresis System (PISCES)

The PISCES instrument is a portable, miniature, modular instrument designed to analyze organic molecular signatures of life. PISCES uses microcapillary electrophoresis (μCE) with laser-induced fluorescence detection (LIFD) to analyze fluorescently-labeled analytes prepared on a multi-layer microfluidic chip. As a modular instrument composed of five independently functioning units, each module can be easily detached from the system and used for subsystem testing in different environments, e.g. low temperature. The pneumatic module contains mechanical and electrical components necessary to control pneumatically-actuated valves for on-chip sample processing. A prototype LabVIEW program and two custom printed circuit boards (PCBs) operate the pneumatics module using an Arduino microcontroller, and a tentative design for the module’s housing has been developed. The high-voltage module contains circuitry required to apply varying electrical potentials to the electrophoretic channel of the microdevice. Work is currently being done to design the circuit and PCB for this module in collaboration with our SBIR partners at Los Gatos Research. The optical electronics module contains the spectrometer, laser, and laser power supply. The mounting components for the electronics and housing for the module have been designed, assembled, and tested. The optical module contains optical components to focus the laser to a 20μm spot in the center of the electrophoretic channel.The housing for this module has been designed and assembled with the aligned optical components inside.

Willis, Peter A.↗
NASA NTRSDate not supplied

Performance Optimization Methods for a Memory-Bound, Unstructured-Grid CFD Application on Massively Parallel GPU Platforms

Computational performance of the FUN3D unstructured-grid computational fluid dynamics (CFD) application on massively parallel GPU environments is memory-bound and highly dependent upon efficient reads from and atomic updates to the irregular cell-, edge-, and node-based data structures. In this talk, we present recent efforts into optimizing select performance-critical kernels on NVIDIA Tesla V100 and A100 GPUs and AMD CDNA MI100 GPUs. A novel use of L2 cache residency controls and asynchronous loads into on-chip shared memory are explored on the A100 GPU for the sparse iterative solver, which is dominated by mixed-precision, sparse matrix vector multiplication. Demonstrations show that these methods improve global memory bandwidth utilization by 13.5% on the A100 GPU. Several techniques are also presented that use registers and/or shared memory to facilitate array transposition and aggregation which combine to reduce the frequency and increase the cache efficiency of floating-point atomic updates to the irregular data structures. These methods are demonstrated to improve the kernel throughput by nearly 500% on select kernels on the AMD MI100 over atomic updates directly to global memory. Overall, both V100 and A100 GPUs outperformed the MI100 GPU on kernels dominated by double-precision atomic updates; however, the techniques demonstrated here reduced the performance gap and improved the MI100 performance.

GPU CPU unstructured CFD memory↗
NASA NTRS2022

Silicon Photonic Transceiver for Spacecraft Navigational Lidar

NASA is developing an entry, descent, and landing (EDL) lidar system, the Navigation Doppler Lidar (NDL), for high-precision landing on the Moon, Mars, and beyond. The current flight NDL systems use 1550 nm fiber-optic components for frequency-modulated continuous wave (FMCW) ranging beyond 5 km, but have reduced performance under vibrational and thermal stresses during EDL. Here we describe recent efforts to develop a breadboard silicon photonic optical transceiver for integration into NDL to reduce instrument size and improve robustness to environment and demonstrate the optical balanced receiver performance during testing with the breadboard NDL unit. Initial testing shows improved suppression of common mode noise by 25 dB over the current receiver, but a 10 dB reduction in signal to noise ratio (SNR) resulting from coupling losses from fiber to the on-chip waveguides. Future work will target reduced coupling loss, hermetic packaging, and co-integration of a single sideband suppressed carrier modulator into the same chip.

Photonic Integrated Circuits↗
NASA NTRSDate not supplied

Learning From Failure: Boosting Cycling Endurance of Optical Phase Change Materials

Chalcogenide phase change materials (PCMs) are a unique class of compounds whose switchable optical and electronic properties have fueled an explosion of emerging applications in microelectronics and microphotonics. Key to any application is the ability of PCMs to reliably switch between crystalline and amorphous states over a large number of cycles. While this issue has been extensively studied in the case of microelectronic memories, current PCM-based optical devices suffer from much inferior endurance. To understand the failure mechanisms limiting endurance of PCMs specifically in microphotonic devices, we have developed an on-chip resistive micro-heater platform and an automatic multi-modal characterization system to analyze cycling performance of optical PCMs. Reversible switching of large-area PCM devices over 50,000 cycles was demonstrated.

Optical phase change material↗
NASA NTRSDate not supplied

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗
NASA NTRSDate not supplied

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗
NASA NTRSDate not supplied

The PCM is Dead! Long Live O-PCM!

The ability to reconfigure the optical behavior of a device enables free-space applications ranging from imaging to sensing and signal control. Such optical devices can be compacted via meta-surfaces, patterned structures with feature sizes below the incident wavelength. Leveraging geometry in addition to material properties and CMOS fabrication techniques has allowed meta-surfaces for lenses, holograms, beam steerers and more. To incorporate multiple optical functions into one device, various methods of device control have been implemented, such as stretching of flexible substrates, tuning the refractive index of the comprising meta-atoms via the electro-optic or the thermo-optic effects, phase transition materials such as VO2 and more. Chalcogenide glasses used as optical phase change materials, such as Ge¬2Sb2Te5 (GST), have gained increased traction in the optics community for potential use in the near infrared (NIR) and mid infrared (MIR) bands, including the telecom bands. Various chalcogenides such as Sb2Se3, Sb2S3, Ge2Sb¬2Se5 and Ge2Sb2Se4Te (GSST) have been investigated due to their broad NIR or MIR transparency window and large changes in refractive index. In their amorphous phase, these materials usually display a lower refractive index and low absorption when compared to their crystalline state which display a higher refractive index and typically larger extinction coefficients. The amorphous-crystalline reversible switching can be done via fast melt-quenching thermal processes triggered by laser or electrical impulses, relying on a substrate as a heat sink. The potential of PCMs in photonic devices can be limited by intrinsic material limitations as well as by device fabrication issues. To explore the cyclability of GSST, a PCM with large refractive index contrast and on-chip electrothermal switching on a silicon-on-insulator platform has been done to analyze potential failure mechanisms from both a material and device perspective. A brief outline of the instrumentation and phase change contrast analysis is provided. Dewetting of the PCM, delamination of and damage in the PECVD SiNx protective layer, elemental migration in the PCM and optical contrast decay have been observed in cycled GSST devices. Guidelines for device performance improvement are proposed, and an improved design with larger endurance is shown in progress.

reconfigurable photonics↗