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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Model-driven mapping onto distributed memory parallel computers

The author addresses the problem of exploiting the parallelism available in a program to efficiently employ the resources of the target machine in the context of building a mapping compiler for a distributed memory parallel machine. He demonstrates the effectiveness of using execution models to select the best mapping technique from among those available for a given program segment on a particular machine. Through analysis of the execution models for several mapping techniques for one class of programs on a linear processor array, it is shown that selecting the best technique for a particular program instance can make a significant difference in performance. On the other hand, the results of benchmarks from a mapping compiler for the Warp systolic array machine show that the execution models considered are accurate enough to select the best mapping technique for a given program.

Sussman, Alan↗
NASA NTRS1980

HP-9825A HFRMP trajectory processor (#TRAJ), detailed description

The computer code for the trajectory processor (#TRAJ) of the high fidelity relative motion program is described. The #TRAJ processor is a 12-degrees-of-freedom trajectory integrator (6 degrees of freedom for each of two vehicles) which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. A listing of the code, coding standards and conventions, detailed flow charts, and discussions of the computational logic are included.

Kindall, S. M.↗
DOE OSTI2021

Locality-aware and sharing-aware cache coherence for collections of processors

A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.

Farmahini Farahani, Amin↗
DOE OSTI2023

Implementation and Demonstration of P4 Software for Improving ICS Protocol Visibility and Control [Slides]

No prior enabling funded work applicable to this proposal. Programming Protocol-independent Packet Processors (P4) is an open source, domain-specific programming language for network switching devices. P4 complements traditional Software Defined Networking (SDN) which is primarily concerned with the management of packets (e.g. routing/dropping decisions) rather than how each packet is processed. The introduction of P4 provided new capabilities (e.g. firewall, load balancing, enhanced security) but has primarily been deployed in data centers. This effort investigates ways to expand P4 into other niches such as ICS networks.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1987

Post-game analysis: An initial experiment for heuristic-based resource management in concurrent systems

In concurrent systems, a major responsibility of the resource management system is to decide how the application program is to be mapped onto the multi-processor. Instead of using abstract program and machine models, a generate-and-test framework known as 'post-game analysis' that is based on data gathered during program execution is proposed. Each iteration consists of (1) (a simulation of) an execution of the program; (2) analysis of the data gathered; and (3) the proposal of a new mapping that would have a smaller execution time. These heuristics are applied to predict execution time changes in response to small perturbations applied to the current mapping. An initial experiment was carried out using simple strategies on 'pipeline-like' applications. The results obtained from four simple strategies demonstrated that for this kind of application, even simple strategies can produce acceptable speed-up with a small number of iterations.

Yan, Jerry C.↗
NASA NTRS1989

Parallel processors and nonlinear structural dynamics algorithms and software

A nonlinear structural dynamics finite element program was developed to run on a shared memory multiprocessor with pipeline processors. The program, WHAMS, was used as a framework for this work. The program employs explicit time integration and has the capability to handle both the nonlinear material behavior and large displacement response of 3-D structures. The elasto-plastic material model uses an isotropic strain hardening law which is input as a piecewise linear function. Geometric nonlinearities are handled by a corotational formulation in which a coordinate system is embedded at the integration point of each element. Currently, the program has an element library consisting of a beam element based on Euler-Bernoulli theory and trianglar and quadrilateral plate element based on Mindlin theory.

Belytschko, Ted↗
NASA NTRS1994

Remote Objects Message Exchange (ROME)

The performance of a single program running on a single processor is limited by the character of the processor. Moreover, the cost and difficulty of developing and sustaining programs tend to increase as their size and complexity increase. Clearly there ought to be some advantage in partitioning powerful application software in relatively small and simple components that can run in parallel on multiple processors; the software should run faster and it should be cheaper and easier to deploy. Remote Objects Message Exchange (ROME) is an attempt to provide a single relatively simple, universally available abstraction for data communication among C++ objects. It aims to enable the C++ application developer to specify objects' interactions with other objects wholly in terms of the application domain, without concern for details of interprocess communication. Every ROME-compliant object is conceptually a network peer of every other, as if each one were (for example) a separate UNIX process.

processors application software data communication↗
NASA NTRS1990

The Use of a Microcomputer Based Array Processor for Real Time Laser Velocimeter Data Processing

The application of an array processor to laser velocimeter data processing is presented. The hardware is described along with the method of parallel programming required by the array processor. A portion of the data processing program is described in detail. The increase in computational speed of a microcomputer equipped with an array processor is illustrated by comparative testing with a minicomputer.

Meyers, James F.↗
DOE OSTI2024

Equilipy

There is high demand for high-throughput calculations of phase equilibria based on the CALPHAD method (CALculation of PHAse Diagram). High-throughput calculations are possible through HPC, currently by a commercial program called Thermo-Calc. However, the number of nodes/processors are limited to the number of purchased license (16 processors per license). This program provides a toolkit for high-throughput calculations of phase equilibria by the CALPHAD method. The program is prepared for Python environment, so that it can be easily installed and used together with other open-source programs. The program can be run in supercomputer.

Kwon, Sunyong [Oak Ridge National Laboratory (ORNL↗
NASA NTRSDate not supplied

Onboard Autonomous Trajectory Planning for Mars Power Descent

In recent years, there has been an increasing interest in space-qualified processors such as multi-core central processing units and graphics processing units that can withstand the adverse effects of space radiation. These processors can allow parallel programming to perform tasks that typically demand high computational power. One can study guidance schemes that can take advantage of these currently developing processors and provide more robust guidance. Software for Multi-model Autonomous Real-time Trajectories (SMART) guidance can identify robust trajectories by running an onboard Monte Carlo analysis. SMART guidance can take advantage of knowledge updates obtained from the onboard sensors, allowing it to consider the off-nominal cases that it would not typically encounter during the offline trajectory analysis. This work uses the SMART guidance for the powered divert at Mars simulation in Program to Optimize and Simulated Trajectories- II.

Pardha Sai Chadalavada↗
NASA NTRSDate not supplied

Onboard Autonomous Trajectory Planning for Mars Power Descent

In recent years, there has been an increasing interest in space-qualified processors such as multi-core central processing units and graphics processing units that can withstand the adverse effects of space radiation. These processors can allow parallel programming to perform tasks that typically demand high computational power. One can study guidance schemes that can take advantage of these currently developing processors and provide more robust guidance. Software for Multi-model Autonomous Real-time Trajectories (SMART) guidance can identify robust trajectories by running an onboard Monte Carlo analysis. SMART guidance can take advantage of knowledge updates obtained from the onboard sensors, allowing it to consider the off-nominal cases that it would not typically encounter during the offline trajectory analysis. This work uses the SMART guidance for the powered divert at Mars simulation in Program to Optimize and Simulated Trajectories- II.

Autonomous Planning↗
NASA NTRS2001

Automation of Data Traffic Control on DSM Architecture

The design of distributed shared memory (DSM) computers liberates users from the duty to distribute data across processors and allows for the incremental development of parallel programs using, for example, OpenMP or Java threads. DSM architecture greatly simplifies the development of parallel programs having good performance on a few processors. However, to achieve a good program scalability on DSM computers requires that the user understand data flow in the application and use various techniques to avoid data traffic congestions. In this paper we discuss a number of such techniques, including data blocking, data placement, data transposition and page size control and evaluate their efficiency on the NAS (NASA Advanced Supercomputing) Parallel Benchmarks. We also present a tool which automates the detection of constructs causing data congestions in Fortran array oriented codes and advises the user on code transformations for improving data traffic in the application.

Frumkin, Michael↗
NASA NTRS1996

Research of TREETOPS Structural Dynamics Controls Simulation Upgrade

Under the provisions of contract number NAS8-40194, which was entitled 'TREETOPS Structural Dynamics and Controls Simulation System Upgrade', Oakwood College contracted to produce an upgrade to the existing TREETOPS suite of analysis tools. This suite includes the main simulation program, TREETOPS, two interactive preprocessors, TREESET and TREEFLX, an interactive post processor, TREEPLOT, and an adjunct program, TREESEL. A 'Software Design Document', which provides descriptions of the argument lists and internal variables for each subroutine in the TREETOPS suite, was established. Additionally, installation guides for both DOS and UNIX platforms were developed. Finally, updated User's Manuals, as well as a Theory Manual, were generated.

Yates, Rose M.↗
NASA NTRS1999

Initial Flight Test of the Production Support Flight Control Computers at NASA Dryden Flight Research Center

The NASA Dryden Flight Research Center has completed the initial flight test of a modified set of F/A-18 flight control computers that gives the aircraft a research control law capability. The production support flight control computers (PSFCC) provide an increased capability for flight research in the control law, handling qualities, and flight systems areas. The PSFCC feature a research flight control processor that is "piggybacked" onto the baseline F/A-18 flight control system. This research processor allows for pilot selection of research control law operation in flight. To validate flight operation, a replication of a standard F/A-18 control law was programmed into the research processor and flight-tested over a limited envelope. This paper provides a brief description of the system, summarizes the initial flight test of the PSFCC, and describes future experiments for the PSFCC.

Carter, John↗
NASA NTRS1992

Initializing Embedded Data Processors From A Single Source

Initial-computer-program-loading system provides startup information to all embedded data processors (EDP's) in general-purpose computer system. Remote processors given image of startup diskette so real local diskette and drive unneeded. System less complex and equipment costs less. Additional benefit, initial program loading tests bus. If boot-up program transmitted correctly, bus assumed to be operating properly.

Chavez, Edward A.↗
NASA NTRS1973

A series-resonant silicon-controlled-rectifier power processor for ion thrusters

A program to develop a power processing system for ion thrusters is presented. Basic operation of the silicon controlled rectifier series inverter circuitry is examined. The approach for synthesizing such circuits into a system which limits the electrical stress levels on the power source, semiconductor switching elements, and the ion thruster load is described. Experimental results are presented for a 2.5-kW breadboard system designed to operate a 20-cm ion thruster.

Shumaker, H. A.↗