Search NASA⌕ Search

SEARCH · Search NASA

Results for “reconfigurable electronics”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

167 records · Page 10

Three-Function Logic Gate Controlled by Analog Voltage

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Zebulum, Ricardo↗

Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Flight Computer↗

New Phase Change Materials for Active Photonics

Phase change materials or PCMs are truly remarkable compounds whose unique switchable properties have fueled an explosion of emerging applications in electronics and photonics. Nonetheless, if we discount their use in optical discs, PCMs’ immense application potential in photonics beyond data recording has only begun to unfold in the past decade. While the material requirements for optical or electronic data storage have been succinctly summarized as five key elements “writability, archival storage, erasability, readability, and cyclability” decades ago, these requirements are not universally relevant to the diverse set of photonic applications now being explored. It also comes as no surprise that existing PCMs, which have been heavily vetted for data storage, are not necessarily the optimal compositions for different use cases in optics and photonics. PCMs with their attributes custom-tailored for specific applications are therefore in demand as phase-change photonics continue to expand. Here we discuss the PCM selection and design strategies specifically for photonic applications as well as our recent work developing active integrated photonic devices and metasurface optics based on new PCMs tailored for photonics.

phase change materials↗

Magnetosphere Dynamics During the 14 November 2012 Storm Inferred from TWINS, AMPERE, Van Allen Probes, and BATS-R-US-CRCM

During the 14 November 2012 geomagnetic storm, the Van Allen Probes spacecraft observed a number of sharp decreases ('dropouts') in particle fluxes for ions and electrons of different energies. In this paper, we investigate the global magnetosphere dynamics and magnetosphere- ionosphere (M-I) coupling during the dropout events using multipoint measurements by Van Allen Probes, TWINS, and AMPERE together with the output of the two-way coupled global BATS-R-US-CRCM model. We find different behavior for two pairs of dropouts. For one pair, the same pattern was repeated: (1) weak nightside Region 1 and 2 Birkeland currents before and during the dropout; (2) intensification of Region 2 currents after the dropout; and (3) a particle injection detected by TWINS after the dropout. The model predicted similar behavior of Birkeland currents. TWINS low-altitude emissions demonstrated high variability during these intervals, indicating high geomagnetic activity in the near-Earth tail region. For the second pair of dropouts, the structure of both Birkeland currents and ENA emissions was relatively stable. The model also showed quasi-stationary behavior of Birkeland currents and simulated ENA emissions with gradual ring current buildup. We confirm that the first pair of dropouts was caused by large-scale motions of the OCB (open-closed boundary) during substorm activity. We show the new result that this OCB motion was associated with global changes in Birkeland (M-I coupling) currents and strong modulation of low-altitude ion precipitation. The second pair of dropouts is the result of smaller OCB disturbances not related to magnetospheric substorms. The local observations of the first pair of dropouts result from a global magnetospheric reconfiguration, which is manifested by ion injections and enhanced ion precipitation detected by TWINS and changes in the structure of Birkeland currents detected by AMPERE. This study demonstrates that multipoint measurements along with the global model results enable the reconstruction of a more complete system-level picture of the dropout events and provides insight into M-I coupling aspects that have not previously been investigated.

Buzulukova, Natalia↗

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗