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At least 181 records · Page 10

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Bouldin, D. L.↗

Enhancement of radiation detection performance with reduction of EH 6/7 deep levels in n-type 4H–SiC through thermal oxidation

We report the effect of EH 6/7 electron trap centers alone on the performance of high-resolution radiation detectors fabricated on n-type 4H–SiC epitaxial layers. A Schottky barrier detector (SBD) and a metal-oxide-semiconductor (MOS) capacitor detector fabricated using two sister samples derived from the same 50 μm 4H–SiC parent wafer exhibited widely different energy resolutions of 0.4% and 0.9% for 5486 keV alpha particles. An equivalent noise charge model analysis ruled out the effect of the detector capacitance and the leakage current on the resolution of the detectors. Deep level transient spectroscopic studies revealed the presence of two trapping centers in each detector within the temperature scan range 240–800 K. The Z 1/2 center, a potential electron trap, was detected in both the detectors in equal concentration, which suggested that the observed difference in the energy resolution is due to the presence of the other defect, the EH 6/7 center, in the SBD. The capture cross section of the EH 6/7 center was calculated to be three orders of magnitude higher than the second defect [a carbon antisite vacancy (CAV) center] observed in the MOS detector with an activation energy of 1.10 eV, which accounted for the enhanced electronic trapping in the SBD leading to its poor energy resolution. It has been proposed that the EH 6/7 centers in the SBD have likely been reconfigured to CAV pairs during the thermal growth of the silicon dioxide layer in the MOS detector. The proposed formation mechanism of CAV, a stable qubit state for quantum information processing, addresses the outstanding questions related to the role of defect dynamics in their formation.

61 RADIATION PROTECTION AND DOSIMETRY↗

The N3/TiO 2 interfacial structure is dependent on the pH conditions during sensitization

The electronic structure of the N3/TiO 2 interface can directly influence the performance of a dye sensitized solar cell (DSSC). Therefore, it is crucial to understand the parameters that control the dye’s orientation on the semiconductor’s surface. A typical step in DSSC fabrication is to submerge the nanoparticulate semiconductor film in a solution containing the dye, the sensitizing solution. The pH of the N3 sensitizing solution determines the distribution of the N3 protonation states that exist in solution. Altering the pH of the sensitizing solution changes the N3 protonation states that exist in solution and, subsequently, the N3 protonation states that anchor to the TiO 2 substrate. We utilize the surface specific technique of heterodyne detected vibrational sum frequency generation spectroscopy to determine the binding geometry of N3 on a TiO 2 surface as a function of the sensitizing solution pH conditions. It is determined that significant reorientation of the dye occurs in pH ≤ 2.0 conditions due to the lack of N3-dye carboxylate anchoring groups participating in adsorption to the TiO 2 substrate. Consequently, the change in molecular geometry is met with a change in the interfacial electronic structure that can hinder electron transfer in DSSC architectures.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Ion-beam sputtering increases solar-cell efficiency

Ion-beam sputtering, fabrication of oxide-semiconductor-on-silicon (OSOS) solar cells, results in cells of 12% efficiency. Ion-beam sputtering technique is compatible with low-cost continuous fabrication and requires no high-temperature processing.

Burk, D. E.↗

Semiconductor apparatus utilizing gradient freeze and liquid-solid techniques

Transition metals of Group VIII (Co, Rh and Ir) have been prepared as semiconductor compounds with the general formula TSb.sub.3. The skutterudite-type crystal lattice structure of these semiconductor compounds and their enhanced thermoelectric properties results in semiconductor materials which may be used in the fabrication of thermoelectric elements to substantially improve the efficiency of the resulting thermoelectric device. Semiconductor materials having the desired skutterudite-type crystal lattice structure may be prepared in accordance with the present invention by using vertical gradient freezing techniques and/or liquid phase sintering techniques. Measurements of electrical and thermal transport properties of selected semiconductor materials prepared in accordance with the present invention, demonstrated high Hall mobilities (up to 1200 cm.sup.2.V.sup.-1.s.sup.-1) and good Seebeck coefficients (up to 150 .mu.VK.sup.-1 between 300.degree. C. and 700.degree. C.). Optimizing the transport properties of semiconductor materials prepared from elemental mixtures Co, Rh, Ir and Sb resulted in a substantial increase in the thermoelectric figure of merit (ZT) at temperatures as high as 400.degree. C. for thermoelectric elements fabricated from such semiconductor materials.

Fleurial, Jean-Pierre↗

High performance thermoelectric materials and methods of preparation

Transition metals (T) of Group VIII (Co, Rh and Ir) have been prepared as semiconductor alloys with Sb having the general formula TSb.sub.3. The skutterudite-type crystal lattice structure of these semiconductor alloys and their enhanced thermoelectric properties results in semiconductor materials which may be used in the fabrication of thermoelectric elements to substantially improve the efficiency of the resulting thermoelectric device. Semiconductor alloys having the desired skutterudite-type crystal lattice structure may be prepared in accordance with the present invention by using vertical gradient freeze techniques, liquid-solid phase sintering techniques, low temperature powder sintering and/or hot-pressing. Measurements of electrical and thermal transport properties of selected semiconductor materials prepared in accordance with the present invention, demonstrated high Hall mobilities (up to 8000 cm.sup.2.V.sup.-1.s.sup.-1), good Seebeck coefficients (up to 400 .mu.VK.sup.-1 between 300.degree. C. and 700.degree. C.), and low thermal conductivities (as low as 15 mW/cmK). Optimizing the transport properties of semiconductor materials prepared from elemental mixtures Co, Rh, Ir and Sb resulted in a two fold increase in the thermoelectric figure of merit (ZT) at temperatures as high as 400.degree. C. for thermoelectric elements fabricated from such semiconductor materials.

Fleurial, Jean-Pierre↗

Formation of internally-confined semiconductor lasers

In technique for fabrication of strip lasers, current constriction is accomplished by diffusing blocking regions into n-type substrate prior to growth. Current flow is controlled by blocking layers, which results in reduction of threshold current and better heat dissipation.

Cannuli, V. M.↗

Rapid Solidification Effects in Additively Manufactured Si and SiGe Compositions

SiGe alloys have a proven track record as robust high-temperature thermoelectric materials, powering NASA missions like SNAP-10A, LES-9, and Voyager 1 and 2. Enhancing thermoelectric efficiency hinges on minimizing thermal conductivity while preserving electrical conductivity. Rapid solidification via LPBF can generate microstructural features such as subgrain cellular boundaries and twinning, which may help reduce thermal conductivity while preserving semiconducting behavior. Here, this study investigates the potential of laser powder bed fusion (LPBF) additive manufacturing to fabricate nanostructured Si and SiGe thermoelectric materials. High cooling rates (10 5 to 10 7 K/s) rates inherent to the LPBF process are conducive to forming such nanostructures. Moreover, this fabrication technique could also be suitable for fabricating complex geometries needed to achieve improved device level performance. Process mapping of commercial Si powder with irregular morphology was first performed to understand the LPBF processing behavior of this semiconductor material. Subsequent studies included in-house synthesized B-doped (p-type) Si7 8 Ge 22 spherical powder that was produced via ultrasonic atomization. Scan strategies involved multiple laser exposures to mitigate solidification cracking: a high density of >98% was achieved, but solidification cracking could not be fully eliminated. Subsequently, a high electrical resistivity (i.e., low conductivity) was observed, but the measured Seebeck coefficient, ∼230 μV/K @ 500 °C, proved that good semiconductor material was being fabricated. A subgrain cellular structure (5–10 μm) was observed as defined by Ge segregation to the intercellular boundaries. The remelting strategies helped lower the cooling rates in processing SiGe, but this still resulted in high residual stresses, which induced a remarkably high density of twins (78–95%) to accommodate the deformation. This unique grain structure offers an avenue for phonon scattering and potential improvements in thermoelectric performance.

figure of merit↗

The 1.083 micron tunable CW semiconductor laser

A tunable CW laser is desired to produce light equivalent to the helium spectral line at 1.08 microns. This laser will serve as an optical pumping source for He-3 and He-4 atoms used in space magnetometers. This light source can be fabricated either as a semiconductor laser diode or a pumped solid state laser. Continuous output power of greater than 10 mW is desired. Semiconductor lasers can be thermally tuned, but must be capable of locking onto the helium resonance lines. Solid state lasers must have efficient pumping sources suitable for space configuration. Additional requirements are as follows: space magnetometer applications will include low mass (less than 0.5 kg), low power consumption (less than 0.75 W), and high stability/reliability for long missions (5-10 years).

Wang, C. S.↗

Development of Polycrystalline Photoelectrodes with Optimum Compositions and Morphologies for Solar Fuel Production via Electrochemical Synthesis (Final Technical Report)

Photoelectrochemical cells (PECs) can utilize solar energy for water splitting to produce H 2 as a clean fuel. The most critical components of a water-splitting PEC are semiconductor electrodes (photoelectrodes) that absorb solar energy to generate photoexcited charge carriers and transport them to the electrode/electrolyte interface for water reduction and oxidation reactions. While efficient PEC hydrogen production has been successfully demonstrated on the laboratory scale, the commercial viability of PECs depends critically on the cost of H 2 produced by the PECs, which is affected by the cost of PEC construction. Therefore, identifying promising inexpensive semiconductor electrodes is important. The goal of this project was to bring an advancement in the synthesis and understanding of inexpensive polycrystalline photoelectrodes based on oxides. Oxide-based semiconductors are inexpensive, easy to fabricate, and relatively more stable in aqueous media compared to other types of semiconductors. This project developed new electrodeposition methods to produce a variety of oxide-based semiconductor electrodes with precisely controlled compositions and morphologies to enhance photon absorption, electron-hole separation, and the use of electrons and holes for desired chemical reactions. The resulting high-quality photoelectrodes were investigated to establish the structure-composition-morphology-photoelectrochemical property relationships to identify the advantages and limitations of each oxide semiconductor system.

14 SOLAR ENERGY↗

Crystalline materials for quantum computing: Semiconductor heterostructures and topological insulators exemplars

Abstract High-purity crystalline solid-state materials play an essential role in various technologies for quantum information processing, from qubits based on spins to topological states. New and improved crystalline materials emerge each year and continue to drive new results in experimental quantum science. This article summarizes the opportunities for a selected class of crystalline materials for qubit technologies based on spins and topological states and the challenges associated with their fabrication. We start by describing semiconductor heterostructures for spin qubits in gate-defined quantum dots and benchmark GaAs, Si, and Ge, the three platforms that demonstrated two-qubit logic. We then examine novel topologically nontrivial materials and structures that might be incorporated into superconducting devices to create topological qubits. We review topological insulator thin films and move onto topological crystalline materials, such as PbSnTe, and its integration with Josephson junctions. We discuss advances in novel and specialized fabrication and characterization techniques to enable these. We conclude by identifying the most promising directions where advances in these material systems will enable progress in qubit technology.

Scappucci, G. (ORCID:0000000325120079)↗

Multi-junction solar cells paving the way for super high-efficiency

In order to realize a clean energy society by using renewable energies, high-performance solar cells are a very attractive proposition. The development of high-performance solar cells offers a promising pathway toward achieving high power per unit cost for many applications. As state-of-the-art of single-junction solar cells are approaching the Shockley–Queisser limit of 32%–33%, an important strategy to raise the efficiency of solar cells further is stacking solar cell materials with different bandgaps to absorb different colors of the solar spectrum. The III–V semiconductor materials provide a relatively convenient system for fabricating multi-junction solar cells providing semiconductor materials that effectively span the solar spectrum as demonstrated by world record efficiencies (39.2% under one-sun and 47.1% under concentration) for six-junction solar cells. This success has inspired attempts to achieve the same with other materials like perovskites for which lower manufacturing costs may be achieved. Recently, Si multi-junction solar cells such as III–V/Si, II–VI/Si, chalcopyrite/Si, and perovskite/Si have become popular and are getting closer to economic competitiveness. Here, we discuss the perspectives of multi-junction solar cells from the viewpoint of efficiency and low-cost potential based on scientific and technological arguments and possible market applications. In addition, this article provides a brief overview of recent developments with respect to III–V multi-junction solar cells, III–V/Si, II–VI/Si, perovskite/Si tandem solar cells, and some new ideas including so-called 3rd generation concepts.

14 SOLAR ENERGY↗

Fabrication of OSOS cells by neutral ion beam sputtering

Oxide semiconductor on silicon (OSOS) solar cells have been fabricated from various indium tin oxide (In2O3)x(SnO2)1-x compositions sputtered onto p-type single crystal silicon substrates with a neutralized argon ion beam. High temperature processing or annealing was not required. The highest efficiency was achieved with x = 0.91 and was 12 percent. The cells are environmentally rugged, chemically stable, and show promise for still higher efficiencies. Moreover, the ion beam sputtering fabrication technique is amenable to low cost, continuous processing.

Burk, D. E.↗

Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

Neudeck, Philip G.↗

High and low threshold P-channel metal oxide semiconductor process and description of microelectronics facility

The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs.

Bouldin, D. L.↗

Scalable Al 2 O 3 –TiO 2 Conductive Oxide Interfaces as Defect Reservoirs for Resistive Switching Devices

Abstract Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here, a simple and scalable material system of conductive oxide interfaces is employed, and their unique properties are leveraged for a new type of resistive switching device. An Al 2 O 3 –TiO 2 ‐based valence‐change resistive switching device, where the conductive oxide interface serves both as the bottom electrode and as a reservoir of defects for switching, is demonstrated. The amorphous–polycrystalline Al 2 O 3 –TiO 2 conductive interface is obtained following the technological path of simplifying the fabrication of the 2D electron gases (2DEGs), making them scalable for practical mass integration. Physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance is combined. The origin of the resistive switching is pinpointed to the conductive oxide interface, which serves both as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence‐change resistive switching devices. The new device, based on scalable and complementary metal–oxide–semiconductor (CMOS)‐technology‐compatible fabrication processes, opens new design spaces toward increased tunability and simplification of the device selection challenge.

36 MATERIALS SCIENCE↗

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were installed in water-cooled jackets, as shown. This was a severe test because the pressure-sensing chips were exposed to the hot combustion gases. Prior to the installation of the SiC pressure sensors, two high-temperature silicon sensors, installed in the same locations, did not survive a single engine run. The durability of the leadless SiC pressure sensor was demonstrated when both SiC sensors operated properly throughout the two runs that were conducted.

Beheim, Glenn M.↗

Method for producing a hybridization of detector array and integrated circuit for readout

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Fossum, Eric R.↗