Search NASA⌕ Search

SEARCH · Search NASA

Results for “silicon devices”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Effects of 22 MeV protons on single junction and silicon controlled rectifiers

The effects of 22-MeV protons on various types of silicon single junction and silicon controlled rectifiers were investigated. The results show that low-leakage devices and silicon controlled rectifiers are the most susceptable to radiation damage. There are also differences noted between single junction rectifiers of the same type made by different manufacturers, which emphasizes the need for better selection of devices used in spacecraft.

Beatty, M. E., III↗
NASA NTRS1989

Spike train generation and current-to-frequency conversion in silicon diodes

A device physics model is developed to analyze spontaneous neuron-like spike train generation in current driven silicon p(+)-n-n(+) devices in cryogenic environments. The model is shown to explain the very high dynamic range (0 to the 7th) current-to-frequency conversion and experimental features of the spike train frequency as a function of input current. The devices are interesting components for implementation of parallel asynchronous processing adjacent to cryogenically cooled focal planes because of their extremely low current and power requirements, their electronic simplicity, and their pulse coding capability, and could be used to form the hardware basis for neural networks which employ biologically plausible means of information coding.

Coon, D. D.↗
NASA NTRS1982

Capacitively-Heated Fluidized Bed

Fluidized-bed chamber in which particles in bed are capacitively heated produces high yields of polycrystalline silicon for semiconductor devices. Deposition of unrecoverable silicon on chamber wall is reduced, and amount of recoverable silicon depositing on seed particles in bed is increased. Particles also have a size and density suitable for direct handling without consolidation, unlike silicon dust produced in heated-wall chambers.

Mchale, E. J.↗
NASA NTRS1983

Sheet silicon cell/module technology

The cost involved in the performance of the standard operations for the manufacture of silicon wafers is insignificant in the case of space photovoltaics applications. It is, however, a decisive factor with respect to terrestrial applications of silicon photovoltaic devices. In 1975, a program was, therefore, begun to develop low cost silicon solar arrays for terrestrial applications. The goal was silicon-based photovoltaic (PV) modules ready for installation at a selling price of $0.50/watt (1975 dollars). Sheet and ribbon silicon growth held out the promise of reduced cost through continuous operation, high material throughput, high material utilization efficiency, and a product whose shape lent itself to the assembly of high packing density modules. Attention is given to ribbon growth technologies, sheet technology generic problems, and ribbon cell and module technology status. It is concluded that the potential for crystalline ribbon silicon appears to be better today than ever before.

Morrison, A. D.↗
DOE OSTI2022

Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC mosfet -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

42 ENGINEERING↗
NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗
DOE OSTI2025

Electronic Melting of Silicon in Nanostructures using X-ray Forbidden Bragg Reflections

Abstract We carried out a short beamtime at the Pohang Accelerator Laboratory x-ray Free Electron Laser to perform a pump-probe (PP) laser excitation diffraction experiment on the silicon (222) forbidden Bragg peak. To limit the x-ray penetration, we used a “device layer” silicon film wafer bonded to a silicon substrate. The sample, specially fabricated by MEMC Electronic Materials, had a Si(100) substrate bonded to a 170 nm Si(100) film rotated at 45° for crystallographic isolation. A second sample was reactive-ion-etched down to 52 nm thickness. In the silicon lattice, the covalent bonds are seen exclusively at the 222 reflection. Upon laser excitation, these electrons are expected to be excited to the valence band on femtosecond electronic time scales. The Si(222) reflection is therefore expected to be extinguished on this fast time scale, while the electron–phonon coupled acoustic response is determined by the lattice dynamics. The latter is determined by the speed of sound over the device thickness, which is in the mid-picosecond range.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS2015

Surface Passivation by Quantum Exclusion Using Multiple Layers

A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes at least two doped layers fabricated using MBE methods. The dopant sheet densities in the doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. The electrically active dopant sheet densities are quite high, reaching more than 1.times.10.sup.14 cm.sup.-2, and locally exceeding 10.sup.22 per cubic centimeter. It has been found that silicon detector devices that have two or more such dopant layers exhibit improved resistance to degradation by UV radiation, at least at wavelengths of 193 nm, as compared to conventional silicon p-on-n devices.

Hoenk, Michael E.↗
NASA NTRS1975

Summary of theoretical and experimental investigation of grating type, silicon photovoltaic cells

Theoretical and experimental aspects are summarized for single crystal, silicon photovoltaic devices made by forming a grating pattern of p/n junctions on the light receiving surface of the base crystal. Based on the general semiconductor equations, a mathematical description is presented for the photovoltaic properties of such grating-like structures in a two dimensional form. The resulting second order elliptical equation is solved by computer modeling to give solutions for various, reasonable, initial values of bulk resistivity, excess carrier concentration, and surface recombination velocity. The validity of the computer model is established by comparison with p/n devices produced by alloying an aluminum grating pattern into the surface of n-type silicon wafers. Current voltage characteristics and spectral response curves are presented for cells of this type constructed on wafers of different resistivities and orientations.

Chen, L. Y.↗
DOE OSTI2024

Nanomanufacturing of Nanophononic Devices: Ultra-high ZT Thermoelectrics for Efficient Conversion of Waste Heat

Fabrication and Characterization Summary: For this program, the team fabricated and tested silicon thermoelectric test structures that experimentally demonstrated record thermal conductivity reduction (> 85 %) without changes in electrical properties (conductivity and Seebeck coefficient). We also demonstrated the highest ever reported energy conversion efficiency for silicon thermoelectric devices. The team developed a design for 1 cm 2 die with thousands of nanophononic metamaterial structures in the form of nanowalled membranes but were unable to solve all fabrication challenges before the end of the program. Multiple aspects of the design were submitted for patent protection. Primary challenges were related to silicon-on-insulator material quality and high-aspect-ratio etching.

30 DIRECT ENERGY CONVERSION↗
NASA NTRS1985

Amorphous silicon photovoltaic modules and test devices design, fabrication and testing

In July of 1984, Hughes and JPL initiated a contract for Hughes to design, fabricate and test 10 thin film Amorphous Silicon (a-Si) photovoltaic power modules. These modules were to be 1 ft x 4 ft in size. They were to be preceded by the delivery of 10 a-Si 4 in. square test devices. This effort is very timely since thin film PV development has progressed to the point where intermediate load power applications are on the horizon. It is important to know if current a-Si submodule design and manufacturing processes yield a product that is compatible with the packaging needed to meet a 20 to 30 year life span expectancy. The term submodule is assigned to an interconnected assembly of 28 a-Si cells deposited on a 1 foot square glass superstrate. These assemblies are equipped with electrical terminations, i.e., copper tabs at the four corners of the inverted submodules. It is these submodules that are to be interconnected and packaged into power modules, as opposed to the interconnected individual crystalline cells packaged into todays PV modules. A discussion of the fabrication methods and results follows.

Vanleeuwen, M.↗
DOE OSTI2020

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Lastly, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

42 ENGINEERING↗
NASA NTRS1993

Nonlinear optical thin films

A focused approach to development and evaluation of organic polymer films for use in optoelectronics is presented. The issues and challenges that are addressed include: (1) material synthesis, purification, and the tailoring of the material properties; (2) deposition of uniform thin films by a variety of methods; (3) characterization of material physical properties (thermal, electrical, optical, and electro-optical); and (4) device fabrication and testing. Photonic materials, devices, and systems were identified as critical technology areas by the Department of Commerce and the Department of Defense. This approach offers strong integration of basic material issues through engineering applications by the development of materials that can be exploited as the active unit in a variety of polymeric thin film devices. Improved materials were developed with unprecedented purity and stability. The absorptive properties can be tailored and controlled to provide significant improvement in propagation losses and nonlinear performance. Furthermore, the materials were incorporated into polymers that are highly compatible with fabrication and patterning processes for integrated optical devices and circuits. By simultaneously addressing the issues of materials development and characterization, keeping device design and fabrication in mind, many obstacles were overcome for implementation of these polymeric materials and devices into systems. We intend to considerably improve the upper use temperature, poling stability, and compatibility with silicon based devices. The principal device application that was targeted is a linear electro-optic modulation etalon. Organic polymers need to be properly designed and coupled with existing integrated circuit technology to create new photonic devices for optical communication, image processing, other laser applications such as harmonic generation, and eventually optical computing. The progression from microscopic sample to a suitable film-forming material in a working device is a complex, multifaceted endeavor. It requires close attention to maintaining the optical properties of the electro-optic active portion of the polymer while manipulating the polymer structure to obtain the desired secondary polymer properties.

Leslie, Thomas M.↗
DOE OSTI2021

Study of an Integration Platform Based on an Adiabatic Active-Layer Waveguide Connection for InP Photonic Device Integration Mirroring That of Heterogeneous Integration on Silicon

In this work, a photonic device integration platform capable of integration of active-passive InP-based photonic devices without the use of material regrowth is introduced. The platform makes use of an adiabatic active-layer waveguide connection (ALWC) to move an optical beam between active and passive devices. The performance of this platform is analyzed using an example made up of four main sections: (1) a fiber coupling section for enabling vertical beam coupling from optical fiber into the photonic chip using a mode-matched surface grating with apodized duty cycles; (2) a transparent waveguide section for realizing passive photonic devices; (3) an adiabatic mode connection structure for moving the optical beam between passive and active device sections; and (4) an active device section for realizing active photonic devices. It is shown that the coupled surface grating, when added with a bottom gold reflector, can achieve a high chip-to-fiber coupling efficiency (CE) of 88.3% at 1550 nm. The adiabatic active-layer mode connection structure has an optical loss of lower than 1% (CE > 99%). The active device section can achieve an optical gain of 20 dB/mm with the use of only 3 quantum wells. The optimized structural parameters of the entire waveguide module are analyzed and discussed.

42 ENGINEERING↗
NASA NTRS2011

Development of an Extreme High Temperature n-type Ohmic Contact to Silicon Carbide

We report on the initial demonstration of a tungsten-nickel (75:25 at. %) ohmic contact to silicon carbide (SiC) that performed for up to fifteen hours of heat treatment in argon at 1000 C. The transfer length method (TLM) test structure was used to evaluate the contacts. Samples showed consistent ohmic behavior with specific contact resistance values averaging 5 x 10-4 -cm2. The development of this contact metallization should allow silicon carbide devices to operate more reliably at the present maximum operating temperature of 600 C while potentially extending operations to 1000 C. Introduction Silicon Carbide (SiC) is widely recognized as one of the materials of choice for high temperature, harsh environment sensors and electronics due to its ability to survive and continue normal operation in such environments [1]. Sensors and electronics in SiC have been developed that are capable of operating at temperatures of 600 oC. However operating these devices at the upper reliability temperature threshold increases the potential for early degradation. Therefore, it is important to raise the reliability temperature ceiling higher, which would assure increased device reliability when operated at nominal temperature. There are also instances that require devices to operate and survive for prolonged periods of time above 600 oC [2, 3]. This is specifically needed in the area of hypersonic flight where robust sensors are needed to monitor vehicle performance at temperature greater than 1000 C, as well as for use in the thermomechanical characterization of high temperature materials (e.g. ceramic matrix composites). While SiC alone can withstand these temperatures, a major challenge is to develop reliable electrical contacts to the device itself in order to facilitate signal extraction

Evans, Laura J.↗
NASA NTRS2009

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Bae, Youngsman↗