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At least 181 records · Page 10

Evaluation of Case Size 0603 BME Ceramic Capacitors

High volumetric efficiency of commercial base metal electrode (BME) ceramic capacitors allows for a substantial reduction of weight and sizes of the parts compared to currently used military grade precious metal electrode (PME) capacitors. Insertion of BME capacitors in space applications requires a thorough analysis of their performance and reliability. In this work, six types of cases size 0603 BME capacitors from three vendors have been evaluated. Three types of multilayer ceramic capacitors (MLCCs) were designed for automotive industry and three types for general purposes. Leakage currents in the capacitors have been measured in a wide range of voltages and temperatures, and measurements of breakdown voltages (VBR) have been used to assess the proportion and severity of defects in the parts. The effect of soldering-related thermal shock stresses was evaluated by analysis of distributions of VBR for parts in 'as is' condition and after terminal solder dip testing at 350 C. Highly Accelerated Life Testing (HALT) at different temperatures was used to assess the activation energy of degradation of leakage currents and predict behavior of the parts at life test and normal operating conditions. To address issues related to rework and manual soldering, capacitors were soldered onto different substrates at different soldering conditions. The results show that contrary to a common assumption that large-size capacitors are mostly vulnerable to soldering stresses, cracking in small size capacitors does happen unless special measures are taken during assembly processes.

testing↗

Board Saver for Use with Developmental FPGAs

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Berkun, Andrew↗

Gamma ray detector modules

A radiation detector assembly has a semiconductor detector array substrate of CdZnTe or CdTe, having a plurality of detector cell pads on a first surface thereof, the pads having a contact metallization and a solder barrier metallization. An interposer card has planar dimensions no larger than planar dimensions of the semiconductor detector array substrate, a plurality of interconnect pads on a first surface thereof, at least one readout semiconductor chip and at least one connector on a second surface thereof, each having planar dimensions no larger than the planar dimensions of the interposer card. Solder columns extend from contacts on the interposer first surface to the plurality of pads on the semiconductor detector array substrate first surface, the solder columns having at least one solder having a melting point or liquidus less than 120 degrees C. An encapsulant is disposed between the interposer circuit card first surface and the semiconductor detector array substrate first surface, encapsulating the solder columns, the encapsulant curing at a temperature no greater than 120 degrees C.

Capote, M. Albert↗

Lead-Free Electronics: Impact for Space Electronics

Pb is used as a constituent in solder alloys used to connect and attach electronic parts to printed wiring boards (PWBs). Similar Pbbearing alloys are electroplated or hot dipped onto the terminations of electronic parts to protect the terminations and make them solderable. Changing to Pb-free solders and termination finishes has introduced significant technical challenges into the supply chain. Tin/lead (Sn/Pb) alloys have been the solders of choice for electronics for more than 50 years. Pb-free solder alloys are available but there is not a plug-in replacement for 60/40 or 63/37 (Sn/Pb) alloys, which have been the industry workhorses.

Sampson, Michael J.↗

Working with Consortia - Advanced Packaging Reliability

Description: Support the responsible NASA official for lead-free solder evaluation. Serve as the NASA technical liaison to the NASA/DoD Pb-free Project. Assure NASA areas of interest are included in JG-PP follow-on work. Support NASA/DoD telcons and face-to-face meetings. Update MSFC lead-free solder lessons learned report. FY10 plans: - Reliability data on lead-free solder applications for various part lead finishes and board finishes. - Update lead-free solder risks and risk mitigation strategies for NASA. - Evaluate lead-free alloy/lead-free finish reliability in design application. - Status CAVE project on Pb-free solder aging effects. - Compile the LTESE flight and bench data.

Blanche, Jim↗

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Ghaffarian, Reza↗

Susceptibility to Cracking of Different Lots of CDR35 Capacitors

On-orbit flight anomalies that occurred after several months of operation were attributed to excessive leakage currents in CDR35 style 0.47 microF 50 V capacitors operating at 10 V. In this work, a lot of capacitors similar to the lot that caused the anomaly have been evaluated in parallel with another lot of similar parts to assess their susceptibility to cracking under manual soldering conditions and get insight into a possible mechanism of failure. Leakage currents in capacitors were monitored at different voltages and environmental conditions before and after terminal solder dip testing that was used to simulate thermal shock during manual soldering. Results of cross-sectioning, acoustic microscopy, and measurements of electrical and mechanical characteristics of the parts have been analyzed, and possible mechanisms of failures considered. It is shown that the susceptibility to cracking and failures caused by manual soldering is lot-related. Recommendations for testing that would help to select lots that are more robust against manual soldering stresses and mitigate the risk of failures suggested.

cracking↗

Environmental effects on silicon solar cells

Test results indicate that solder coating cells produces protective or deleterious effect, depending on the environment. Major problem for solder coated cells is in control of solder thickness and uniformity. Problem area for non-solder coated cells is not identified.

Berman, P. A.↗

The relationship between reliability and bonding techniques in hybrid microcircuits

Differential thermal expansion was shown to be responsible for many observed failures in ceramic chip capacitors mounted on alumina substrates. It is shown that the mounting techniques used in bonding the capacitors have a marked effect upon the thermally induced mechanical stress and thus the failure rate. A mathematical analysis was conducted of a composite model of the capacitor-substrate system to predict the magnitude of thermally induced stresses. It was experimentally observed that the stresses in more compliant bonding systems such as soft lead tin and indium solders are significantly lower than those in hard solder and epoxy systems. The marked dependence upon heating and cooling rate was proven to be a determining factor in the prediction of failure solder systems. It was found that the harder or higher melting solders are less susceptible to thermal cycling effects but that they are more likely to fail during initial processing operations. Strain gage techniques were used to determine thermally induced expansion stresses of the capacitors and the alumina substrates. The compliance of the different bonding mediums was determined. From the data obtained, several recommendations are made concerning the optimum bonding system for the achievement of maximum reliability.

Caruso, S. V.↗

The relationship between reliability and bonding techniques in hybrid systems

Differential thermal expansion has been shown to be responsible for many observed failures in ceramic chip capacitors mounted on alumina substrates. The present work has shown that the mounting techniques used in bonding the capacitors have a marked effect upon the thermally induced mechanical stress and thus the failure rate. A mathematical analysis of a composite model of the capacitor-substrate system to predict the magnitude of thermally induced stresses has been conducted. It has been observed that the stresses in more compliant bonding systems such as soft lead/tin and indium solders are significantly lower than those in hard solder and epoxy systems. The marked dependence upon heating and cooling rate has proven to be a determining factor in the prediction of failure in both the indium and tin/lead solder systems. This study has shown that the harder or higher melting solders are less susceptible to thermal cycling effects but that they are more likely to fail during initial processing operations. Recommendations are made concerning the optimum bonding system for the achievement of maximum reliability.

Kinser, D. L.↗

Assembling Multicolor Printing Plates

Improved joining method uses wave-soldering techniques developed for integrated-circuit-board assemblies. Thermosetting plastic is replaced by wave soldering, which applies a thin even coat of solder to mating copper surfaces. This is done after ink holes and channels have been protected by water-soluble, high-temperature solder mask which prevents wetting and clogging.

Waters, W. J.↗

Multicolor printing plate joining

An upper plate having ink flow channels and a lower plate having a multicolored pattern are joined. The joining is accomplished without clogging any ink flow paths. A pattern having different colored parts and apertures is formed in a lower plate. Ink flow channels each having respective ink input ports are formed in an upper plate. The ink flow channels are coated with solder mask and the bottom of the upper plate is then coated with solder. The upper and lower plates are pressed together at from 2 to 5 psi and heated to a temperature of from 295 F to 750 F or enough to melt the solder. After the plates have cooled and the pressure is released, the solder mask is removed from the interior passageways by means of a liquid solvent.

Waters, W. J.↗

Space flight printed wiring board measling investigation

A flight printed wiring board (PWB) for a satellite project was observed to have a high incidence of measling. Other PWB's produced for the program by the same manufacturer did not exhibit the degree of measling as did the 'measle-prone' board. Measling susceptibility during hand soldering and measling effects on PWB insulation resistance were investigated for three production PWB's. Measling resistance was significantly different between the three boards: the 'worst' exhibited five times the number of measles as the 'best' board. 'Severe' measling (that which is likely to affect board reliability) did not exist on the 'best' board, even under extreme soldering conditions (399 degrees C for 12-15 sec.), whereas the 'worst' board showed an average of one 'severe' measle for every two pads under more normal soldering conditions (288-343 degrees C for 2-5 sec.). Both soldering time and temperature affected measling, with time having a slightly greater influence (2 percent versus 12 percent). Measling effects on PWB insulation resistance were inconclusive. These were evaluated by in situ resistance measurements on the same three boards at elevated temperature and humidity. The measured resistance for all three boards decreased for exposures greater than 50 degrees C and 50 percent relative humidity. The 'measle-prone' board showed a resistance decrease at only 25 degrees C and 50 percent relative humidity. However, no definitive difference was detected between measled and not-measled (control) samples. The boards evaluated were production boards, so the effect of interlayer traces connecting the plated-through holes was not controlled. It is likely the resistance measurements were over different volumes of PWB laminate, which would account for the widely varying resistances measured. Thermomechanical measurements on board laminate materials did not reveal any differences attributed to measling. Differences in glass transition temperature were significantly different when measured by DTA, but not by SDT. Laminate thermal expansion differences were significant for the 35 degrees C evaluations, but not for any higher temperatures.

Thomas, Walter B., III↗

Current Space Station Experiments Investigating Component Level Electronics Repair

The Soldering in a Reduced Gravity Experiment (SoRGE) and Component Repair Experiment (CRE)-1 are tests performed on the International Space Station to determine the techniques, tools, and training necessary to allow future crews to perform manual electronics repairs at the component level. SoRGE provides information on the formation and internal structure of through-hole solder joints, illustrating the challenges and implications of soldering in reduced gravity. SoRGE showed a significant increase in internal void defects for joints formed in low gravity compared to normal gravity. Methods for mitigating these void defects were evaluated using a modified soldering process. CRE-1 demonstrated the removal, cleaning, and replacement of electronics components by manual means on functional circuit boards. The majority of components successful passed a post-repair functional test demonstrating the feasibility of component-level repair within the confines of a spacecraft. Together, these tasks provide information to recommend material and tool improvements, training improvements, and future work to help enable electronics repairs in future space missions.

Easton, John W.↗

System for Packaging Planetary Samples for Return to Earth

A system is proposed for packaging material samples on a remote planet (especially Mars) in sealed sample tubes in preparation for later return to Earth. The sample tubes (Figure 1) would comprise (1) tubes initially having open tops and closed bottoms; (2) small, bellows-like collapsible bodies inside the tubes at their bottoms; and (3) plugs to be eventually used to close the tops of the tubes. The top inner surface of each tube would be coated with solder. The side of each plug, which would fit snugly into a tube, would feature a solder-filled ring groove. The system would include equipment for storing, manipulating, filling, and sealing the tubes. The containerization system (see Figure 2) will be organized in stations and will include: the storage station, the loading station, and the heating station. These stations can be structured in circular or linear pattern to minimize the manipulator complexity, allowing for compact design and mass efficiency. The manipulation of the sample tube between stations is done by a simple manipulator arm. The storage station contains the unloaded sample tubes and the plugs before sealing as well as the sealed sample tubes with samples after loading and sealing. The chambers at the storage station also allow for plug insertion into the sample tube. At the loading station the sample is poured or inserted into the sample tube and then the tube is topped off. At the heating station the plug is heated so the solder ring melts and seals the plug to the sample tube. The process is performed as follows: Each tube is filled or slightly overfilled with sample material and the excess sample material is wiped off the top. Then, the plug is inserted into the top section of the tube packing the sample material against the collapsible bellowslike body allowing the accommodation of the sample volume. The plug and the top of the tube are heated momentarily to melt the solder in order to seal the tube.

Badescu, Mircea↗

Thermally Conductive Metal-Tube/Carbon-Composite Joints

An improved method of fabricating joints between metal and carbon-fiber-based composite materials in lightweight radiators and heat sinks has been devised. Carbon-fiber-based composite materials have been used in such heat-transfer devices because they offer a combination of high thermal conductivity and low mass density. Metal tubes are typically used to carry heat-transfer fluids to and from such heat-transfer devices. The present fabrication method helps to ensure that the joints between the metal tubes and the composite-material parts in such heat-transfer devices have both (1) the relatively high thermal conductances needed for efficient transfer of heat and (2) the flexibility needed to accommodate differences among thermal expansions of dissimilar materials in operation over wide temperature ranges. Techniques used previously to join metal tubes with carbon-fiber-based composite parts have included press fitting and bonding with epoxy. Both of these prior techniques have been found to yield joints characterized by relatively high thermal resistances. The present method involves the use of a solder (63 percent Sn, 37 percent Pb) to form a highly thermally conductive joint between a metal tube and a carbon-fiber-based composite structure. Ordinarily, the large differences among the coefficients of thermal expansion of the metal tube, solder, and carbon-fiber-based composite would cause the solder to pull away from the composite upon post-fabrication cooldown from the molten state. In the present method, the structure of the solder is modified (see figure) to enable it to deform readily to accommodate the differential thermal expansion.

Copeland, Robert J.↗

NASA-DoD Lead-Free Electronics Project

In response to concerns about risks from lead-free induced faults to high reliability products, NASA has initiated a multi-year project to provide manufacturers and users with data to clarify the risks of lead-free materials in their products. The project will also be of interest to component manufacturers supplying to high reliability markets. The project was launched in November 2006. The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: - Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of lead-free alloys - Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of mixed alloys, lead component finish/lead-free solder and lead-free component finish/SnPb solder.

Kessel, Kurt R.↗

NASA-DoD Lead-Free Electronics Project

In response to concerns about risks from lead-free induced faults to high reliability products, NASA has initiated a multi-year project to provide manufacturers and users with data to clarify the risks of lead-free materials in their products. The project will also be of interest to component manufacturers supplying to high reliability markets. The project was launched in November 2006. The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: (1) Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIP]) assembled and reworked with solder interconnects consisting of lead-free alloys (2) Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of mixed alloys, lead component finish/lead-free solder and lead-free component finish/SnPb solder

Kessel, Kurt↗