Radiation Hard CMOS Sensors for Detector at High Energy Colliders
In this project we developed a radiation hard CMOS sensor architecture for High Energy Colliders. The key accomplishments were: 1. Developed a sensor architecture to support very high occupancy rate and hit rates 2. Developed, simulated (TCAD), and fabricated 20 different types of pixelated test structures for the quadruple well high resistivity substrate process. Measured performance of these pixel test structures; Dark currents were found to be close to physical limits; and Quantum efficiency were found to be close to ideal as well 3. Defined the scope for the PDK for the quadruple well process on high resistivity silicon Highlights of the new architecture are: Readout of pixel arrays with reconstruction efficiency >99% at hit rates of 500 MHits/cm 2 and array occupancy of 0.2%; Minimization of in-pixel signal storage requirement (data will be read out at frame rates of 1MHz); Low power dissipation through integration of fragmented projection architecture (Minimum analog power dissipation); Pixel array level data reduction (Hit location is encoded through shape of sub-block projections); Programmable resolution and frame rate (Pixels can be binned to increase frame rate); Minimum data overhead, encoded projection results for all sub-blocks are read out without location information