SEARCH · Search NASA

Results for “Arithmetic”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 199 records · Page 11

All sources NASA NTRS DOE OSTI

NASA NTRS1978

A comparison of two recent approaches to machine parameterization for mathematical software

Two proposals for expressing the dependence of numerical software on the environment are examined. The approaches are briefly summarized and the differences and similarities are discussed. One proposal characterizes the dependence of the software on the machine architecture essentially in terms of the representation of floating point entities in the machine. The second characterizes the dependence of the software on the environment in terms of models both of the floating point numbers and of the behavior of the arithmetic unit of the machine.

Smith, B. T.↗

NASA NTRS1978

UNIX as an environment for producing numerical software

The UNIX operating system supports a number of software tools; a mathematical equation-setting language, a phototypesetting language, a FORTRAN preprocessor language, a text editor, and a command interpreter. The design, implementation, documentation, and maintenance of a portable FORTRAN test of the floating-point arithmetic unit of a computer is used to illustrate these tools at work.

Schryer, N. L.↗

NASA NTRS1979

Faster fourier transformation: The algorithm of S. Winograd

The new DFT algorithm of S. Winograd is developed and presented in detail. This is an algorithm which uses about 1/5 of the number of multiplications used by the Cooley-Tukey algorithm and is applicable to any order which is a product of relatively prime factors from the following list: 2,3,4,5,7,8,9,16. The algorithm is presented in terms of a series of tableaus which are convenient, compact, graphical representations of the sequence of arithmetic operations in the corresponding parts of the algorithm. Using these in conjunction with included Tables makes it relatively easy to apply the algorithm and evaluate its performance.

Zohar, S.↗

NASA NTRS1977

High-speed computerized tomography

The development of a high-speed reconstruction processor and a channelized architecture to use with a high-resolution tomographic unit is discussed with attention to the convolution reconstruction algorithm. By means of this algorithm, input data and intermediate result precision required throughout the algorithm execution have been studied with computer simulation using profile data derived from mathematically simulated test objects and experimental animal data. A prototype section for a highly parallel all-digital system executes 60 million arithmetic operations per second, and the full-scale version is expected to reconstruct 500 to 1000 cross sections per second.

Swartzlander, E. E., Jr.↗

NASA NTRS1978

Floating-point system quantization errors in digital control systems

This paper considers digital controllers (filters) operating in floating-point arithmetic in either open-loop or closed-loop systems. A quantization error analysis technique is developed, and is implemented by a digital computer program that is based on a digital simulation of the system. The program can be integrated into existing digital simulations of a system.

Phillips, C. L.↗

NASA NTRS1978

Fixed-point error analysis of Winograd Fourier transform algorithms

The quantization error introduced by the Winograd Fourier transform algorithm (WFTA) when implemented in fixed-point arithmetic is studied and compared with that of the fast Fourier transform (FFT). The effect of ordering the computational modules and the relative contributions of data quantization error and coefficient quantization error are determined. In addition, the quantization error introduced by the Good-Winograd (GW) algorithm, which uses Good's prime-factor decomposition for the discrete Fourier transform (DFT) together with Winograd's short length DFT algorithms, is studied. Error introduced by the WFTA is, in all cases, worse than that of the FFT. In general, the WFTA requires one or two more bits for data representation to give an error similar to that of the FFT. Error introduced by the GW algorithm is approximately the same as that of the FFT.

Patterson, R. W.↗

NASA NTRS1979

Flight test of a VTOL digital autoland system along complex trajectories

The objective of this research is the development and flight test of a digital multi-rate VTOL autoland system. This autoland system provided the NASA/Army Fly-by-Wire CH-47 helicopter with an automatic 4-D trajectory following and landing capability. Flight tests were conducted along complex trajectories with descending, turning, and decelerating segments. The flight software consists of a trajectory generator and guidance algorithm operating at two iterations per second and a set of sensor filters and an advanced controller operating at 10 iterations per second. This low iteration rate digital controller has a proportional-integral structure that provides an autotrim function. The control gains, scheduled as a function of flight condition, are updated every two seconds. All flight software, except input/output routines, are coded in FORTRAN using floating point arithmetic and are exercised in a ROLM 1664 flight computer. The flight software, the ground and flight hardware, the autoland system's position tracking performance, and the controller's velocity and heading tracking performance are presented.

Downing, D. R.↗

NASA NTRS1979

Logarithmic spiral grids for image processing

A picture digitization grid based on logarithmic spirals rather than Cartesian coordinates is presented. Expressing this curvilinear grid as a conformal exponential mapping reveals useful image processing properties. The mapping induces a computational simplification that suggests parallel architectures in which most geometric transformations are effected by data shifting in memory rather than arithmetic on coordinates. These include fast, parallel noise-free rotation, scaling, and some projective transformations of pixel defined images. Conformality of the mapping preserves local picture-processing operations such as edge detection.

Weiman, C. F. R.↗

NASA NTRS1980

A polymorphic reconfigurable emulator for parallel simulation

Microprocessor and arithmetic support chip technology was applied to the design of a reconfigurable emulator for real time flight simulation. The system developed consists of master control system to perform all man machine interactions and to configure the hardware to emulate a given aircraft, and numerous slave compute modules (SCM) which comprise the parallel computational units. It is shown that all parts of the state equations can be worked on simultaneously but that the algebraic equations cannot (unless they are slowly varying). Attempts to obtain algorithms that will allow parellel updates are reported. The word length and step size to be used in the SCM's is determined and the architecture of the hardware and software is described.

Parrish, E. A., Jr.↗

NASA NTRS1980

Computer program documentation D1FLTD to drive SINDA boundary nodes: User's guide

The thermal model correlation process begins when measured thermocouple data is available from the orbital flight tests of the shuttle. For this effort, it is necessary to convert some of the system improved numerical differencing analyzer (SINDA) diffusion or arithmetic nodes to boundary nodes and then drive these boundary nodes to the temperature profile of a flight measurement. An efficient way to provide this capability within the SINDA and OFT software systems is to provide a new SINDA routine, D1FLTD, for use in VARIABLES 1 of SINDA, to access the processed (word-addressable) orbital data reduction center flight data and store the appropriate measurement temperature in the desired SINDA temperature location. The ODRC flight data that is to be used for driving the boundary nodes must be assigned a logical unit number and must reside on a word-addressable file. The user must also provide two SINDA constants for the word positions of the first and last words of the temperature record for each measurement identifier (MID), i.e. each call to D1FLTD, used in the model. D1FLTD is then called from the VARIABLES 1 block to obtain the SINDA boundary node temperature for any MID on the file at any time point.

Damico, S. J.↗

NASA NTRS1979

A microprocessor-based cardiotachometer

The development of a highly accurate and reliable cardiotachometer for measuring the heart rate of test subjects is discussed. It measures heart rate over the range of 30 to 250 beats/minute and gives instantaneous (beat to beat) updates on the system output so that occasional noise artifacts or ectopic beats could be more easily identified except that occasional missed beats caused by switching ECG leads should not cause a change in the output. The cardiotachometer uses an improved analog filter and R-wave detector and an Intel 8080A microprocessor to handle all of the logic and arithmetic necessary. By using the microprocessor, future hardware modifications could easily be made if functional changes were needed.

Donaldson, J. A.↗

NASA NTRS1980

Nonanalytic function generation routines for 16-bit microprocessors

Interpolation techniques for three types (univariate, bivariate, and map) of nonanalytic functions are described. These interpolation techniques are then implemented in scaled fraction arithmetic on a representative 16 bit microprocessor. A FORTRAN program is described that facilitates the scaling, documentation, and organization of data for use by these routines. Listings of all these programs are included in an appendix.

Soeder, J. F.↗

NASA NTRS1979

VLSI system for synthetic aperture radar /SAR/ processing

The paper discusses an SAR problem based on actual requirements set forth by NASA for a spaceborne application. The requirements for high resolution and high quality necessitate a data sampling rate of 7.5 MHz. For each data value 1,025 4-bit complex multiply + add operations are needed, which is equivalent to 7.7 GHz complex multiply + add operation rate. Since this rate is much too high for general purpose systems, a special-purpose device was sought. This paper discusses two architectures based on parallel operation of 1,025 identical cells, each of which is capable of performing arithmetic, storage, and several control operations. The operation rate in each device is only 7.5 MHz, which is quite manageable, especially with the help of a substantial degree of pipelining. A computational-mathematical analysis is used as a primary tool for evaluating the design and some of its tradeoffs. Two different approaches are discussed and compared; both are based on having 1,025 identical cells working in parallel, but differ in their dual approaches to the flow of data.

Cohen, D.↗

NASA NTRS1979

The Massively Parallel Processor and its applications

A long-term experimental development program conducted at Goddard Space Flight Center to implement an ultrahigh-speed data processing system known as the Massively Parallel Processor (MPP) is described. The MPP is a single instruction multiple data stream computer designed to perform logical, integer, and floating point arithmetic operations on variable word length data. Information is presented on system architecture, the system configuration, the array unit architecture, individual processing units, and expected operating rates for several image processing applications (including the processing of Landsat data).

Strong, J. P.↗

NASA NTRS1980

G-cueing microcontroller (a microprocessor application in simulators)

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Horattas, C. G.↗

NASA NTRS1980

Microprocessor software applications for flight training simulators

The g cueing system software design and implementation in the dual microprocessor system of the F-15 operational flight training simulator g cueing system is presented. The software is structured in the two microcomputers such that one serves as a controller performing all logical functions and interface with the host computer system while the other serves as an arithmetic unit performing all mathematical functions.

Leavy, W. P.↗

NASA NTRS1980

Application of software technology to a future spacecraft computer design

A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

Labaugh, R. J.↗

NASA NTRS1979

Fiber optic combiner and duplicator

The investigation of the possible development of two optical devices, one to take two images as inputs and to present their arithmetic sum as a single output, the other to take one image as input and present two identical images as outputs is described. Significant engineering time was invested in establishing precision fiber optics drawing capabilities, real time monitoring of the fiber size and exact measuring of fiber optics ribbons. Various assembly procedures and tooling designs were investigated and prototype models were built and evaluated that established technical assurance that the device was feasible and could be fabricated. Although the interleaver specification in its entirety was not achieved, the techniques developed in the course of the program improved the quality of images transmitted by fiber optic arrays by at least an order of magnitude. These techniques are already being applied to the manufacture of precise fiber optic components.

Source record↗