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NASA NTRS1983

Node Synchronization for the Viterbi Decoder

At very low signal to noise ratios such as those that Voyager 2 will encounter at Uranus, the performance of the Reed-Solomon/Viterbi concatenated coding system could be seriously degraded by loss of node synchronization by the Viterbi decoder. This problem is described and now it can be almost completely avoided with a simple outboard hardware ""node synchronizer''. This device makes statistical decisions about node sync based on the hard quantized undecoded data stream. In a worst case Voyager-like environment, our method will detect and correct a true loss of node sync (thought to be a very rate event) within several hundred bits; many of these false alarms for our technique is on the order several years.

Lorden, G.↗

NASA NTRS1984

Node synchronization for the Viterbi decoder

At very low signal to noise ratios such as those that Voyager 2 will encounter at Uranus, the performance of the Reed-Solomon/Viterbi concatenated coding system could be seriously degraded by loss of node synchronization by the Viterbi decoder. This problem is described and now it can be almost completely avoided with a simple outboard hardware 'node synchronizer'. This device makes statistical decisions about node sync based on the hard quantized undecoded data stream. In a worst case Voyager-like environment, our method will detect and correct a true loss of node sync (thought to be a very rare event) within several hundred bits; many of these false alarms for our technique is on the order several years. Previously announced in STAR as N83-28028

Lorden, G.↗

NASA NTRS2006

A Low Noise, Microprocessor-Controlled, Internally Digitizing Rotating-Vane Electric Field Mill for Airborne Platforms

This paper reports on a new generation of aircraft-based rotating-vane style electric field mills designed and built at NASA's Marshall Spaceflight Center. The mills have individual microprocessors that digitize the electric field signal at the mill and respond to commands from the data system computer. The mills are very sensitive (1 V/m per bit), have a wide dynamic range (115 dB), and are very low noise (+/-1 LSB). Mounted on an aircraft, these mills can measure fields from +/-1 V/m to +/-500 kV/m. Once-per-second commanding from the data collection computer to each mill allows for precise timing and synchronization. The mills can also be commanded to execute a self-calibration in flight, which is done periodically to monitor the status and health of each mill.

Bateman, M. G.↗

NASA NTRS2000

Parallel integrated frame synchronizer chip

A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.

Ghuman, Parminder Singh↗

NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗

NASA NTRS2011

Frame Synchronization Without Attached Sync Markers

We describe a method to synchronize codeword frames without making use of attached synchronization markers (ASMs). Instead, the synchronizer identifies the code structure present in the received symbols, by operating the decoder for a handful of iterations at each possible symbol offset and forming an appropriate metric. This method is computationally more complex and doesn't perform as well as frame synchronizers that utilize an ASM; nevertheless, the new synchronizer acquires frame synchronization in about two seconds when using a 600 kbps software decoder, and would take about 15 milliseconds on prototype hardware. It also eliminates the need for the ASMs, which is an attractive feature for short uplink codes whose coding gain would be diminished by the overheard of ASM bits. The lack of ASMs also would simplify clock distribution for the AR4JA low-density parity-check (LDPC) codes and adds a small amount to the coding gain as well (up to 0.2 dB).

Hamkins, Jon↗

NASA NTRS2006

MISSE 1 and 2 Tray Temperature Measurements

The Materials International Space Station Experiment (MISSE 1 & 2) was deployed August 10,2001 and retrieved July 30,2005. This experiment is a co-operative endeavor by NASA-LaRC. NASA-GRC, NASA-MSFC, NASA-JSC, the Materials Laboratory at the Air Force Research Laboratory, and the Boeing Phantom Works. The objective of the experiment is to evaluate performance, stability, and long term survivability of materials and components planned for use by NASA and DOD on future LEO, synchronous orbit, and interplanetary space missions. Temperature is an important parameter in the evaluation of space environmental effects on materials. The MISSE 1 & 2 had autonomous temperature data loggers to measure the temperature of each of the four experiment trays. The MISSE tray-temperature data loggers have one external thermistor data channel, and a 12 bit digital converter. The MISSE experiment trays were exposed to the ISS space environment for nearly four times the nominal design lifetime for this experiment. Nevertheless, all of the data loggers provided useful temperature measurements of MISSE. The temperature measurement system has been discussed in a previous paper. This paper presents temperature measurements of MISSE payload experiment carriers (PECs) 1 and 2 experiment trays.

Harvey, Gale A.↗

NASA NTRS1991

A bandwidth efficient coding scheme for the Hubble Space Telescope

As a demonstration of the performance capabilities of trellis codes using multidimensional signal sets, a Viterbi decoder was designed. The choice of code was based on two factors. The first factor was its application as a possible replacement for the coding scheme currently used on the Hubble Space Telescope (HST). The HST at present uses the rate 1/3 nu = 6 (with 2 (exp nu) = 64 states) convolutional code with Binary Phase Shift Keying (BPSK) modulation. With the modulator restricted to a 3 Msym/s, this implies a data rate of only 1 Mbit/s, since the bandwidth efficiency K = 1/3 bit/sym. This is a very bandwidth inefficient scheme, although the system has the advantage of simplicity and large coding gain. The basic requirement from NASA was for a scheme that has as large a K as possible. Since a satellite channel was being used, 8PSK modulation was selected. This allows a K of between 2 and 3 bit/sym. The next influencing factor was INTELSAT's intention of transmitting the SONET 155.52 Mbit/s standard data rate over the 72 MHz transponders on its satellites. This requires a bandwidth efficiency of around 2.5 bit/sym. A Reed-Solomon block code is used as an outer code to give very low bit error rates (BER). A 16 state rate 5/6, 2.5 bit/sym, 4D-8PSK trellis code was selected. This code has reasonable complexity and has a coding gain of 4.8 dB compared to uncoded 8PSK (2). This trellis code also has the advantage that it is 45 deg rotationally invariant. This means that the decoder needs only to synchronize to one of the two naturally mapped 8PSK signals in the signal set.

Pietrobon, Steven S.↗

NASA NTRS1993

A high-speed lossless data compression system for space applications

This paper reports on the integration of a lossless data compression/decompression chipset into a space data system architecture. For its compression engine, the data system incorporates the Universal Source Encoder (USE) designed for the NASA/Goddard Space Flight Center. Currently, the data compression testbed generates video frames consisting of 512 lines of 512 pixels having 8-bit resolution. Each image is passed through the USE where the lines are internally partitioned into 16-word blocks. These blocks are adaptively encoded across widely varying entropy levels using a Rice 12-option set coding algorithm. The current system operates at an Input/Output rate of 10 Msamples/s or 80 Mbits/s for each buffered input line. Frame and line synchronization for each image are maintained through the use of uniquely decodable command words. Length information of each variable length compressed image line is also included in the output stream. The data and command information are passed to the next stage of the system architecture through a serial fiber-optic transmitter. The initial segment of this stage consists of packetizer hardware which adds an appropriate CCSDS header to the received source data. An uncompressed mode is optionally available to pass image lines directly to the packetizer hardware. A data decompression testbed has also been developed to confirm the data compression operation.

Miko, Joe↗

NASA NTRS1980

Open-loop nanosecond-synchronization for wideband satellite communications

A synchronization technique for use with an onboard processing satellite communication system is discussed. The satellite oscillator is used both as the system time reference and as the frequency source for all downlink carriers and data clocks. Downlink timing is established at each system earth terminal through a combination of carrier and data-clock tracking and a downlink timing epoch signal consisting of one bit per TDMA data burst. Uplink timing is established by an open-loop range prediction process using precision ephemerides calculated and distributed by the central control station. Overall timing accuracy of the uplink signal at the satellite receiver of + or - 7 nanoseconds permits unambiguous identification of each data bit position in a 128 Mbps TDMA burst. This is accomplished by means of simple, inexpensive terminal hardware using available crystal oscillators for time/frequency references and digital synthesis techniques that may be implemented in digital LSI chips.

Holmes, W. M., Jr.↗

NASA NTRS1972

Pulsed plasma solid propellant microthruster for the synchronous meteorological satellite. Task 4: Engineering model fabrication and test report

Two flight prototype solid propellant pulsed plasma microthruster propulsion systems for the SMS satellite were fabricated, assembled and tested. The propulsion system is a completely self contained system requiring only three electrical inputs to operate: a 29.4 volt power source, a 28 volt enable signal and a 50 millsec long command fire signal that can be applied at any rate from 50 ppm to 110 ppm. The thrust level can be varied over a range 2.2 to 1 at constant impulse bit amplitude. By controlling the duration of the 28 volt enable either steady state thrust or a series of discrete impulse bits can be generated. A new technique of capacitor charging was implemented to reduce high voltage stress on energy storage capacitors.

Guman, W. J.↗

NASA NTRS1992

The VLBA correlator: Real-time in the distributed era

The correlator is the signal processing engine of the Very Long Baseline Array (VLBA). Radio signals are recorded on special wideband (128 Mb/s) digital recorders at the 10 telescopes, with sampling times controlled by hydrogen maser clocks. The magnetic tapes are shipped to the Array Operations Center in Socorro, New Mexico, where they are played back simultaneously into the correlator. Real-time software and firmware controls the playback drives to achieve synchronization, compute models of the wavefront delay, control the numerous modules of the correlator, and record FITS files of the fringe visibilities at the back-end of the correlator. In addition to the more than 3000 custom VLSI chips which handle the massive data flow of the signal processing, the correlator contains a total of more than 100 programmable computers, 8-, 16- and 32-bit CPUs. Code is downloaded into front-end CPU's dependent on operating mode. Low-level code is assembly language, high-level code is C running under a RT OS. We use VxWorks on Motorola MVME147 CPU's. Code development is on a complex of SPARC workstations connected to the RT CPU's by Ethernet. The overall management of the correlation process is dependent on a database management system. We use Ingres running on a Sparcstation-2. We transfer logging information from the database of the VLBA Monitor and Control System to our database using Ingres/NET. Job scripts are computed and are transferred to the real-time computers using NFS, and correlation job execution logs and status flow back by the route. Operator status and control displays use windows on workstations, interfaced to the real-time processes by network protocols. The extensive network protocol support provided by VxWorks is invaluable. The VLBA Correlator's dependence on network protocols is an example of the radical transformation of the real-time world over the past five years. Real-time is becoming more like conventional computing. Paradoxically, 'conventional' computing is also adopting practices from the real-time world: semaphores, shared memory, light-weight threads, and concurrency. This appears to be a convergence of thinking.

Wells, D. C.↗

NASA NTRS2004

Reduction of Phase Ambiguity in an Offset-QPSK Receiver

Proposed modifications of an offset-quadri-phase-shift keying (offset-QPSK) transmitter and receiver would reduce the amount of signal processing that must be done in the receiver to resolve the QPSK fourfold phase ambiguity. Resolution of the phase ambiguity is necessary in order to synchronize, with the received carrier signal, the signal generated by a local oscillator in a carrier-tracking loop in the receiver. Without resolution of the fourfold phase ambiguity, the loop could lock to any of four possible phase points, only one of which has the proper phase relationship with the carrier. The proposal applies, more specifically, to an offset-QPSK receiver that contains a carrier-tracking loop like that shown in Figure 1. This carrier-tracking loop does not resolve or reduce the phase ambiguity. A carrier-tracking loop of a different design optimized for the reception of offset QPSK could reduce the phase ambiguity from fourfold to twofold, but would be more complex. Alternatively, one could resolve the fourfold phase ambiguity by use of differential coding in the transmitter, at a cost of reduced power efficiency. The proposed modifications would make it possible to reduce the fourfold phase ambiguity to twofold, with no loss in power efficiency and only relatively simple additional signal-processing steps in the transmitter and receiver. The twofold phase ambiguity would then be resolved by use of a unique synchronization word, as is commonly done in binary phase-shift keying (BPSK). Although the mathematical and signal-processing principles underlying the modifications are too complex to explain in detail here, the modifications themselves would be relatively simple and are best described with the help of simple block diagrams (see Figure 2). In the transmitter, one would add a unit that would periodically invert bits going into the QPSK modulator; in the receiver, one would add a unit that would effect different but corresponding inversions of bits coming out of the QPSK demodulator. The net effect of all the inversions would be that depending on which lock point the carrier-tracking loop had selected, all the output bits would be either inverted or non-inverted together; hence, the ambiguity would be reduced from fourfold to twofold, as desired.

Berner, Jeff↗

NASA NTRS1980

Satellite communication performance evaluation: Computational techniques based on moments

Computational techniques that efficiently compute bit error probabilities when only moments of the various interference random variables are available are presented. The approach taken is a generalization of the well known Gauss-Quadrature rules used for numerically evaluating single or multiple integrals. In what follows, basic algorithms are developed. Some of its properties and generalizations are shown and its many potential applications are described. Some typical interference scenarios for which the results are particularly applicable include: intentional jamming, adjacent and cochannel interferences; radar pulses (RFI); multipath; and intersymbol interference. While the examples presented stress evaluation of bit error probilities in uncoded digital communication systems, the moment techniques can also be applied to the evaluation of other parameters, such as computational cutoff rate under both normal and mismatched receiver cases in coded systems. Another important application is the determination of the probability distributions of the output of a discrete time dynamical system. This type of model occurs widely in control systems, queueing systems, and synchronization systems (e.g., discrete phase locked loops).

Omura, J. K.↗

NASA NTRS2013

Closed-Loop Analysis of Soft Decisions for Serial Links

We describe the benefit of using closed-loop measurements for a radio receiver paired with a counterpart transmitter. We show that real-time analysis of the soft decision output of a receiver can provide rich and relevant insight far beyond the traditional hard-decision bit error rate (BER) test statistic. We describe a Soft Decision Analyzer (SDA) implementation for closed-loop measurements on single- or dual- (orthogonal) channel serial data communication links. The analyzer has been used to identify, quantify, and prioritize contributors to implementation loss in live-time during the development of software defined radios. This test technique gains importance as modern receivers are providing soft decision symbol synchronization as radio links are challenged to push more data and more protocol overhead through noisier channels, and software-defined radios (SDRs) use error-correction codes that approach Shannon's theoretical limit of performance.

Lansdowne, Chatwin A.↗

NASA NTRS2013

Soft Decision Analyzer

Lansdowne, Chatwin↗

NASA NTRS1990

Multi-level modulation codes and multi-stage decoding

Multi-level method is a powerful technique for constructing bandwidth efficient modulation codes. It allows the construction of modulation codes systematically with arbitrary large minimum squared Euclidean distance from component codes in conjunction with proper bits-to-signal mapping. If the component codes are chosen properly, the resultant modulation code not only has good minimum squared Euclidean distance but is also rich in structural properties such as: linear structure, phase invariant property, and trellis structure. A modulation code with linear structure has invariant distance distribution. Phase invariant property is useful in resolving carrier-phase ambiguity and ensuring rapid carrier-phase resynchronization after temporary loss of synchronization. It the component codes have trellis structure, the resultant multi-level modulation code also has trellis structure. Trellis structure allows decoding of a multi-level modulation code with the soft-decision Viterbi decoding algorithm. Furthermore, the multi-level structure allows decoding of a multi-level modulation code with the multi-stage decoding. This type of decoding reduces the decoding complexity. Multi-stage decoding is not optimum even though the decoding of each component is optimum. Based on the analysis and simulation results, the difference in error performance between the optimum decoding of the overall multi-level modulation code and the suboptimum multi-stage decoding of the code is very little, a fraction of dB loss.

Lin, Shu↗

NASA NTRS1987

A prototype 4800 bps voice terminal for the mobile satellite experiment

The authors report the final stage of a research project for the NASA mobile satellite experiment (MSAT-X). The work has resulted in two alternative coding techniques which have achieved good communications quality at 4.8 kb/s while tolerating vehicle noise, fading, and a fairly high-error-rate, bursty channel. The authors have constructed a circuit board based on three AT&T 32-bit floating-point DSP32 digital signal processors (DSP) and providing both excess processing power and considerable flexibility for handling different variations of the algorithms. A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. Mounted on a wirewrapped card, the prototype's circuit footprint amounts to only 225 cm2 and consumes about 13 W of power. A description is given of the architecture, signal processing and communication functions, circuitry, and firmware of the prototype. Issues such as synchronization, framing, error control, and modem interface are also addressed.

Chan, Wai-Yip↗