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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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187 records · Page 11
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Here, sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin.

1/f noise↗
DOE OSTI2020

The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL

The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Metaplastic and energy-efficient biocompatible graphene artificial synaptic transistors for enhanced accuracy neuromorphic computing

CMOS-based computing systems that employ the von Neumann architecture are relatively limited when it comes to parallel data storage and processing. In contrast, the human brain is a living computational signal processing unit that operates with extreme parallelism and energy efficiency. Although numerous neuromorphic electronic devices have emerged in the last decade, most of them are rigid or contain materials that are toxic to biological systems. In this work, we report on biocompatible bilayer graphene-based artificial synaptic transistors (BLAST) capable of mimicking synaptic behavior. The BLAST devices leverage a dry ion-selective membrane, enabling long-term potentiation, with ~50 aJ/µm 2 switching energy efficiency, at least an order of magnitude lower than previous reports on two-dimensional material-based artificial synapses. The devices show unique metaplasticity, a useful feature for generalizable deep neural networks, and we demonstrate that metaplastic BLASTs outperform ideal linear synapses in classic image classification tasks. With switching energy well below the 1 fJ energy estimated per biological synapse, the proposed devices are powerful candidates for bio-interfaced online learning, bridging the gap between artificial and biological neural networks.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS

One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Developing time-resolved x-ray diffraction diagnostics at the National Ignition Facility (invited)

As part of a program to measure phase transition timescales in materials under dynamic compression, we have designed new x-ray imaging diagnostics to record multiple x-ray diffraction measurements during a single laser-driven experiment. Our design places several ns-gated hybrid CMOS (hCMOS) sensors within a few cm of a laser-driven target. The sensors must be protected from an extremely harsh environment, including debris, electromagnetic pulses, and unconverted laser light. Another key challenge is reducing the x-ray background relative to the faint diffraction signal. Building on the success of our predecessor (Target Diffraction In Situ), we implemented a staged approach to platform development. First, we built a demonstration diagnostic (Gated Diffraction Development Diagnostic) with two hCMOS sensors to confirm we could adequately protect them from the harsh environment and also acquire acceptable diffraction data. This allowed the team to quickly assess the risks and address the most significant challenges. Here, we also collected scientifically useful data during development. Leveraging what we learned, we recently developed a much more ambitious instrument (Flexible Imaging Diffraction Diagnostic for Laser Experiments) that can field up to eight hCMOS sensors in a flexible geometry and participate in back-to-back shots at the National Ignition Facility (NIF). The design also allows for future iterations, such as faster hCMOS sensors and an embedded x-ray streak camera. The enhanced capabilities of the new instrument required a much more complex design, and the unexpected issues encountered on the first few shots at NIF remind us that complexity has consequences. Our progress in addressing these challenges is described herein, as is our current focus on improving data quality by reducing x-ray background and quantifying the uncertainties of our diffraction measurements.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Advancing microelectronics through nanoscale science: A perspective on needs and opportunities from the nanoscale science research centers

Microelectronics are the cornerstone of the modern world, enhancing our daily lives by providing services such as communications and datacenters. These resources are accessible thanks to the continual pursuit of a deeper understanding of the chemical and physical phenomena underlying the materials synthesis approaches and fabrication processes used to create microelectronic components and subsequently the components' responses to electrical, optical, and other stimuli that are utilized within microelectronic systems. Today, further development of microelectronics requires multidisciplinary expertise across scientific disciplines and fields of study—synthesis, materials characterization, nanoscale fabrication, and performance characterization—with focus placed on comprehending the nanoscale forms and features of microelectronic components. The Nanoscale Science Research Centers (NSRCs) are Department of Energy, Office of Science user facilities that support the international scientific community in advancing nanoscale science and technology. As a key component of the U.S. Government's National Nanotechnology Initiative, the NSRCs enable transformative discoveries by providing world-class facilities, expertise, and collaborative opportunities. Here, in this perspective, we showcase a non-exhaustive cross-section of the capabilities housed at and developed by the NSRCs and their user communities to address fundamental synthesis, metrology, fabrication, and performance considerations toward advancing the development of new microelectronics. Finally, we provide a timely outlook on the next major areas of necessary development in nanoscale sciences to continue the innovation of microelectronics into the next generation.

2D materials↗