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At least 199 records · Page 11

Development of an LSI maximum-likelihood convolutional decoder for advanced forward error correction capability on the NASA 30/20 GHz program

The particular coding option identified as providing the best level of coding gain performance in an LSI-efficient implementation was the optimal constraint length five, rate one-half convolutional code. To determine the specific set of design parameters which optimally matches this decoder to the LSI constraints, a breadboard MCD (maximum-likelihood convolutional decoder) was fabricated and used to generate detailed performance trade-off data. The extensive performance testing data gathered during this design tradeoff study are summarized, and the functional and physical MCD chip characteristics are presented.

Clark, R. T.↗

A low-power, high-throughput maximum-likelihood convolutional decoder chip for NASA's 30/20 GHz program

It is pointed out that the NASA 30/20 GHz program will place in geosynchronous orbit a technically advanced communication satellite which can process time-division multiple access (TDMA) information bursts with a data throughput in excess of 4 GBPS. To guarantee acceptable data quality during periods of signal attenuation it will be necessary to provide a significant forward error correction (FEC) capability. Convolutional decoding (utilizing the maximum-likelihood techniques) was identified as the most attractive FEC strategy. Design trade-offs regarding a maximum-likelihood convolutional decoder (MCD) in a single-chip CMOS implementation are discussed.

Mccallister, R. D.↗

New syndrome decoder for (n, 1) convolutional codes

The letter presents a new syndrome decoding algorithm for the (n, 1) convolutional codes (CC) that is different and simpler than the previous syndrome decoding algorithm of Schalkwijk and Vinck. The new technique uses the general solution of the polynomial linear Diophantine equation for the error polynomial vector E(D). A recursive, Viterbi-like, algorithm is developed to find the minimum weight error vector E(D). An example is given for the binary nonsystematic (2, 1) CC.

Reed, I. S.↗

Simulations for Full Unit-memory and Partial Unit-memory Convolutional Codes with Real-time Minimal-byte-error Probability Decoding Algorithm

A program which was written to simulate Real Time Minimal-Byte-Error Probability (RTMBEP) decoding of full unit-memory (FUM) convolutional codes on a 3-bit quantized AWGN channel is described. This program was used to compute the symbol-error probability of FUM codes and to determine the signal to noise (SNR) required to achieve a bit error rate (BER) of 10 to the minus 6th power for corresponding concatenated systems. A (6,6/30) FUM code, 6-bit Reed-Solomon code combination was found to achieve the required BER at a SNR of 1.886 dB. The RTMBEP algorithm was then modified for decoding partial unit-memory (PUM) convolutional codes. A simulation program was also written to simulate the symbol-error probability of these codes.

Vo, Q. D.↗

Performance analysis of the word synchronization properties of the outer code in a TDRSS decoder

A self-synchronizing coding scheme for NASA's TDRSS satellite system is a concatenation of a (2,1,7) inner convolutional code with a (255,223) Reed-Solomon outer code. Both symbol and word synchronization are achieved without requiring that any additional symbols be transmitted. An important parameter which determines the performance of the word sync procedure is the ratio of the decoding failure probability to the undetected error probability. Ideally, the former should be as small as possible compared to the latter when the error correcting capability of the code is exceeded. A computer simulation of a (255,223) Reed-Solomon code as carried out. Results for decoding failure probability and for undetected error probability are tabulated and compared.

Costello, D. J., Jr.↗

Decoding: Software implementations

The motivation to use phase coded observations for the stratosphere-troposphere region is discussed. Previous work using hardware correlators to decode the received signal is referred. An alternative technique using software to decode the signal samples is described, and results of the implementation are presented.

Loriot, G. B.↗

Novel applications of the NASA/GSFC Viterbi decoder hardware simulator

The NASA/GSFC developed an all digital, real time, programmable Viterbi decoder simulator operating at rates up to 6 Msps. With this simulator, the bit error rate (BER) performance of convolutionally encoded/Viterbi decoded Shuttle-TDRSS return link channels under pulsed radio frequency interference (RFI) conditions has been predicted. The principles of the simulator are described with special emphasis on the channel simulator and the essential interaction between CLASS software and the simulator. The sensitivity of coded BER as function of several illustrative RFI parameters is discussed for two typical Shuttle-TDRSS return link configurations.

Walvis, D. J. M.↗

Self-synchronizing outer codes for the TDRSS decoder

In this paper, various aspects of developing a self-synchronizing coding system are discussed for NASA's TDRSS satellite system. The coding system used is a concatenation of a (2, 1, 7) inner convolutional code with a (255,223) Reed-Solomon outer code. The goal is to design the decoder in such a way that both symbol and word synchronization are achieved for the outer code without the need for any separate synchronization patten. The system proposed in this paper uses the properties of the inner (Viterbi) decoder to provide symbol synchronization for the outer code, and maintains word synchronization by making use of a coset code of the Reed-Solomon code.

Lin, S.↗

Simplified Decoding of Convolutional Codes

Some complicated intermediate steps shortened or eliminated. Decoding of convolutional error-correcting digital codes simplified by new errortrellis syndrome technique. In new technique, syndrome vector not computed. Instead, advantage taken of newly-derived mathematical identities simplify decision tree, folding it back on itself into form called "error trellis." This trellis graph of all path solutions of syndrome equations. Each path through trellis corresponds to specific set of decisions as to received digits. Existing decoding algorithms combined with new mathematical identities reduce number of combinations of errors considered and enable computation of correction vector directly from data and check bits as received.

Truong, T. K.↗

Decoding convolutionally encoded images

Maximum Likelihood Convolutional Decoding, which is used by the Deep Space Network for short constraint-length convolutional codes, assumes that all strings of information bits are equally likely. In some cases, like image data, this is not the case. The use of information about an adjacent pixel in decoding convolutionally encoded Voyager images is examined. It is discovered that, in a region of interest, as much as 2 dB may be gained.

Pitt, G. H., III↗

Image statistics decoding for convolutional codes

It is a fact that adjacent pixels in a Voyager image are very similar in grey level. This fact can be used in conjunction with the Maximum-Likelihood Convolutional Decoder (MCD) to decrease the error rate when decoding a picture from Voyager. Implementing this idea would require no changes in the Voyager spacecraft and could be used as a backup to the current system without too much expenditure, so the feasibility of it and the possible gains for Voyager were investigated. Simulations have shown that the gain could be as much as 2 dB at certain error rates, and experiments with real data inspired new ideas on ways to get the most information possible out of the received symbol stream.

Pitt, G. H., III↗

Single-Chip VLSI Reed-Solomon Decoder

Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.

Shao, Howard M.↗

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

Shao, H. M.↗

A lower bound for the decoder error probability of the linear MDS code

A lower bound for the decoder error probability (P sub E (u)) of a linear maximum distance separable (MDS) code is derived by counting the dominant types of decoding words around code words. It is shown that the lower bound derived is similar in form, and close numerically, to the upper bound derived.

Cheung, K.-M.↗

A software simulation study of the long constraint length VLSI Viterbi decoder

A software simulation of long constraint length Viterbi decoders was developed. This software closely follows the hardware architecture that was chosen for the Very Large Scale Integration implementation. The program is used to validate the design of the decoder and to generate test vectors for the VLSI circuits.

Arnold, S.↗

Decoding of 1/2-rate (24,12) Golay codes

A decoding method for a (23,12) Golay code is extended to the important 1/2-rate (24,12) Golay code so that three errors can be corrected and four errors can be detected. It is shown that the method can be extended to any decoding method which can correct three errors in the (23,12) Golay code.

Truong, T.-K.↗

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

Shao, Howard M.↗

Multi-level trellis coded modulation and multi-stage decoding

Several constructions for multi-level trellis codes are presented and many codes with better performance than previously known codes are found. These codes provide a flexible trade-off between coding gain, decoding complexity, and decoding delay. New multi-level trellis coded modulation schemes using generalized set partitioning methods are developed for Quadrature Amplitude Modulation (QAM) and Phase Shift Keying (PSK) signal sets. New rotationally invariant multi-level trellis codes which can be combined with differential encoding to resolve phase ambiguity are presented.

Costello, Daniel J., Jr.↗