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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

FLASH: FPGA-Accelerated Smart Switches with GCN Case Study

Some communication switches, e.g., the Mellanox SHArP and those in the IBM BlueGene clusters, are augmented to process packets at the application level with fixed-function collectives. This approach, however, lacks flexibility, which limits their applicability in diverse and dynamic workloads. Recently, a new type of programmable packet processor, which uses high-level languages, e.g., P4, has emerged as possible candidates. P4-based switches, however, fall short in certain applications, including machine learning, where capabilities not currently supported by P4 are needed. These include more complex calculation, such as sparse computation and fused multiply-accumulate, data-intensive floating point operations, data reuse, and significant memory. The problem addressed here is that such a switch augmentation needs to support: a large amount of state, significant flexible compute capability, and ease of programming, all while maintaining full functionality, including ensuring high throughput, and demonstrating utility. In this work, we propose a programmable look-aside-type accelerator that can be embedded into, or attached to, existing communication switch pipelines and that is capable of processing packets at line-rate. The proposed in-switch accelerator is based on mixing an ISA (subset of RISC-V instructions) with dataflow graphs (found in CGRAs). To augment performance, vector instructions are also supported. To facilitate usability, we have developed a complete toolchain to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator. While this approach is flexible enough to support various workloads, in this paper, we consider Graph Convolutional Networks (GCNs) as a case study. Experimental results show that this approach considerably improves the performance of distributed GCN applications.

Haghi, Pouya↗
DOE OSTI2021

Impacts of Substrate Thinning on FPGA Performance and Reliability [Slides]

Substrate thinning is necessary in devices with flip-chip BGA packages to enable both radiation testing and component qualification and high-spatial resolution beam-based failure analysis methods. We investigated three factors affecting device performance: subsurface damage from the thinning process, reduced heat spreading in thin substrates, and changes in device switching speed. We conclude subsurface damage to crystalline Si caused by the thinning process is removable with sufficient SiO 2 slurry polishing. Local temperature differences increase minimally in devices thinned to 3 μm. Compressive stress in the Si increases globally after device thinning and leads to slowing of ring oscillator frequency by about 0.5% compared to full-thickness devices. Future work will include extending the results to submicron Si thickness values, which also has important benefits for failure analysis, debug, and security assessments. We also plan to extend this type of work to other FPGAs and other devices like memory and processors.

36 MATERIALS SCIENCE↗