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Results for “LOGICAL DESIGN”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Microwave brightness temperature of a windblown sea

A mathematical model is developed for the apparent temperature of the sea at all microwave frequencies. The model is a numerical model in which both the clear water structure and white water are accounted for as a function of wind speed. The model produces results similar to Stogryn's model at 19.35 GHz for wind speeds less than 8 m/sec; it can use radiosonde data to calculate atmospheric effects and can incorporate an empirically determined antenna gain pattern. The corresponding computer program is of modular design and the logic of the main program is capable of treating a horizontally inhomogeneous surface or atmosphere. It is shown that a variation of microwave brightness temperature with zenith angle is necessary to produce the wind sensitivity of the horizontally polarized brightness temperature; the variation of sky temperature with frequency is sufficient to produce a frequency dependent wind sensitivity.

Hall, F. G.↗
NASA NTRS1972

Aerospace vehicle synthesis program

A modified version of the Aerospace Vehicle Synthesis Program (VSP) to simulate a space shuttle on the computer is presented. The effects of various changes such as payload weight, and orbital velocity can be determined along with minimum costs in vehicle design. The program logic, and weight estimating equations are discussed, and an example case of a solid propellant boosted, drop tank orbiter is included to indicate the type of results produced by the VSP.

Source record↗
NASA NTRS1975

Design of a modular digital computer system, CDRL no. D001, final design plan

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics.

Easton, R. A.↗
NASA NTRS1975

Landsat 2 on-board computer

The Landsat Spacecraft Project (formerly known as ERTS) was based essentially on the use of Nimbus spacecraft hardware. It was soon recognized that the availability of only 30 stored command locations (which were sufficient for the Nimbus mission) would limit the operation of the Landsat 1 mission with much higher power sensors, recorders, and wideband communications being cycled on and off throughout the orbit. The solution described is a simple memory with hard wired logic, of a design that can interface with the existing hardware, without modifications. The design was implemented using an existing APO (Advanced Onboard Processor) and a 4096 word X 18 bit plated wire memory. (The AOP has been subsequently designated the NASA Standard Spacecraft Computer.)

Lesko, J. G., Jr.↗
NASA NTRS1979

Development of CMOS integrated circuits

Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

Bertino, F.↗
NASA NTRS1979

The Massively Parallel Processor and its applications

A long-term experimental development program conducted at Goddard Space Flight Center to implement an ultrahigh-speed data processing system known as the Massively Parallel Processor (MPP) is described. The MPP is a single instruction multiple data stream computer designed to perform logical, integer, and floating point arithmetic operations on variable word length data. Information is presented on system architecture, the system configuration, the array unit architecture, individual processing units, and expected operating rates for several image processing applications (including the processing of Landsat data).

Strong, J. P.↗
NASA NTRS1985

Challenges in the development of the orbiter active thermal control subsystem

A number of major challenges were faced in the design and development of the Orbiter Active Thermal Control Subsystem (ATCS). At the system level, the initial challenges were to define an approach that would interface dual Freon coolant loops with multiple coolant loops from other vehicle subsystems with the lowest weight penalty to the Orbiter; and to provide highly responsive vehicle heat rejection throughout all of the Orbiter mission phases. Optimized heat exchangers, representing an advance in the state-of-the-art in heat exchanger design, were developed to transfer heat between the orbiter Freon coolant loops and five other vehicle systems. Flash evaporation was selected as a highly efficient and responsive means for cooling the Orbiter Freon loops during ascent and entry. The Flash Evaporator Subsystem (FES) utilizes cyclic water spray cooling in a chamber maintained at or below the water triple point pressure. A summary of the basic heat transfer research conducted to identify the fundamental heat transfer processes involved in water spray cooling in support of the FES design is given. The high fidelity dynamic analytical model of the FES that was generated to aid in the design of control logic, evaluate performance and simulate ground test and flight anomalies is discussed. A description of the FES and Integrated ATCS testing conducted in the SESL chamber A at NASA-JSC is also presented.

Nason, J. R.↗
NASA NTRS1985

Fault detection and accommodation testing on an F100 engine in an F-15 airplane

The fault detection and accommodation (FDA) methodology for digital engine-control systems may range from simple comparisons of redundant parameters to the more complex and sophisticated observer models of the entire engine system. Evaluations of the various FDA schemes are done using analytical methods, simulation, and limited-altitude-facility testing. Flight testing of the FDA logic has been minimal because of the difficulty of inducing realistic faults in flight. A flight program was conducted to evaluate the fault detection and accommodation capability of a digital electronic engine control in an F-15 aircraft. The objective of the flight program was to induce selected faults and evaluate the resulting actions of the digital engine controller. Comparisons were made between the flight results and predictions. Several anomalies were found in flight and during the ground test. Simulation results showed that the inducement of dual pressure failures was not feasible since the FDA logic was not designed to accommodate these types of failures.

Myers, L. P.↗
NASA NTRS1985

Fault detection and accommodation testing on an F100 engine in an F-15 airplane

The fault detection and accommodation (FDA) methods that can be used for digital engine control systems are presently subjected to a flight test program in the case of the F-15 fighter's F100 engine electronic controls, inducing selected faults and then evaluating the resulting digital engine control responses. In general, flight test results were found to compare well with both ground tests and predictions. It is noted that the inducement of dual-pressure failures was not feasible, since FDA logic was not designed to accommodate them.

Myers, L. P.↗
NASA NTRS1987

An expert system for air traffic control system

The objective was to design a control logic which automates all or part of the guidance function for air traffic control systems. Particular interest was focused on automation of the terminal area control system. A preliminary study was done on the development of an expert system. The system may be used to assist controllers by providing them with feasible options in guiding each aircraft in the control area to its desired destination.

Sensui, Takashi↗
NASA NTRS1988

VLSI high speed packet processor

The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a packet processor card utilizing semicustom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multichannel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the packet processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semicustom VLSI logic.

Grebowsky, Gerald J.↗
NASA NTRS1990

Efficient algorithms for dilated mappings of binary trees

The problem is addressed to find a 1-1 mapping of the vertices of a binary tree onto those of a target binary tree such that the son of a node on the first binary tree is mapped onto a descendent of the image of that node in the second binary tree. There are two natural measures of the cost of this mapping, namely the dilation cost, i.e., the maximum distance in the target binary tree between the images of vertices that are adjacent in the original tree. The other measure, expansion cost, is defined as the number of extra nodes/edges to be added to the target binary tree in order to ensure a 1-1 mapping. An efficient algorithm to find a mapping of one binary tree onto another is described. It is shown that it is possible to minimize one cost of mapping at the expense of the other. This problem arises when designing pipelined arithmetic logic units (ALU) for special purpose computers. The pipeline is composed of ALU chips connected in the form of a binary tree. The operands to the pipeline can be supplied to the leaf nodes of the binary tree which then process and pass the results up to their parents. The final result is available at the root. As each new application may require a distinct nesting of operations, it is useful to be able to find a good mapping of a new binary tree over existing ALU tree. Another problem arises if every distinct required binary tree is known beforehand. Here it is useful to hardwire the pipeline in the form of a minimal supertree that contains all required binary trees.

Iqbal, M. Ashraf↗
NASA NTRS1992

High-speed architecture for the decoding of trellis-coded modulation

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

Osborne, William P.↗
NASA NTRS1995

ASIC For Complex Fixed-Point Arithmetic

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

Petilli, Stephen G.↗
NASA NTRS2013

Orion MPCV Touchdown Detection Threshold Development and Testing

A robust method of detecting Orion Multi-Purpose Crew Vehicle (MPCV) splashdown is necessary to ensure crew and hardware safety during descent and after touchdown. The proposed method uses a triple redundant system to inhibit Reaction Control System (RCS) thruster firings, detach parachute risers from the vehicle, and transition to the post-landing segment of the Flight Software (FSW). An in-depth trade study was completed to determine optimal characteristics of the touchdown detection method resulting in an algorithm monitoring filtered, lever-arm corrected, 200 Hz Inertial Measurement Unit (IMU) vehicle acceleration magnitude data against a tunable threshold using persistence counter logic. Following the design of the algorithm, high fidelity environment and vehicle simulations, coupled with the actual vehicle FSW, were used to tune the acceleration threshold and persistence counter value to result in adequate performance in detecting touchdown and sufficient safety margin against early detection while descending under parachutes. An analytical approach including Kriging and adaptive sampling allowed for a sufficient number of finite element analysis (FEA) impact simulations to be completed using minimal computation time. The combination of a persistence counter of 10 and an acceleration threshold of approximately 57.3 ft/s2 resulted in an impact performance factor of safety (FOS) of 1.0 and a safety FOS of approximately 2.6 for touchdown declaration. An RCS termination acceleration threshold of approximately 53.1 ft/s(exp)2 with a persistence counter of 10 resulted in an increased impact performance FOS of 1.2 at the expense of a lowered under-parachutes safety factor of 2.2. The resulting tuned algorithm was then tested on data from eight Capsule Parachute Assembly System (CPAS) flight tests, showing an experimental minimum safety FOS of 6.1. The formulated touchdown detection algorithm will be flown on the Orion MPCV FSW during the Exploration Flight Test 1 (EFT-1) mission in the second half of 2014.

Daum, Jared↗
NASA NTRS2022

Compressed CO2 Hard Rock Drill for Mars

We have developed a down-the-hole (DTH) rotary-percussive drill prototype that could operate on compressed Mars atmospheric CO2 gas with a wireline drilling approach. This technology addresses a need for more aggressive sampling and drilling techniques, for both scientific purposes and to obtain In-Situ Resource Utilization (ISRU) resources for future NASA missions and human crew support. Using a spool of lightweight, high-pressure capillary, a DTH drill assembly would be moved in and out of the hole that could be a kilometer or more in depth. The CO2 drill is designed so that Mars atmospheric CO2 could be collected, compressed, and supplied down the hole and routed through microducts, valves, and reservoirs for the purpose of controlling miniature mechanical actuation in the assembly. By using compressed CO2, the drill system avoids the need for heavy electrical cabling and actuator systems or a liquid media for carrying away particulates as is typically used in terrestrial drilling systems. Instead, the liquid CO2 that powers the drill expands to a gas and could be channeled around the drill housing to carry cuttings to be collected in a bailing bucket. Where terrestrial systems often use drill depth vs time as a metric, a Mars drilling system would need to be extremely low mass, but would have no need to perform under tight schedules. In this paper, we will document our trade studies, progression for the design of microduct logic verified through multiple generations of prototypes, and provide predictive performance data on energy consumption, hole depth, and drill time.

Wilcox, Brian↗
NASA NTRS2022

Compressed CO2 Hard Rock Drill for Mars

We have developed a down-the-hole (DTH) rotary-percussive drill prototype that could operate on compressed Mars atmospheric CO2 gas with a wireline drilling approach. This technology addresses a need for more aggressive sampling and drilling techniques, for both scientific purposes and to obtain In-Situ Resource Utilization (ISRU) resources for future NASA missions and human crew support. Using a spool of lightweight, high-pressure capillary, a DTH drill assembly would be moved in and out of the hole that could be a kilometer or more in depth. The CO2 drill is designed so that Mars atmospheric CO2 could be collected, compressed, and supplied down the hole and routed through microducts, valves, and reservoirs for the purpose of controlling miniature mechanical actuation in the assembly. By using compressed CO2, the drill system avoids the need for heavy electrical cabling and actuator systems or a liquid media for carrying away particulates as is typically used in terrestrial drilling systems. Instead, the liquid CO2 that powers the drill expands to a gas and could be channeled around the drill housing to carry cuttings to be collected in a bailing bucket. Where terrestrial systems often use drill depth vs time as a metric, a Mars drilling system would need to be extremely low mass, but would have no need to perform under tight schedules. In this paper, we will document our trade studies, progression for the design of microduct logic verified through multiple generations of prototypes, and provide predictive performance data on energy consumption, hole depth, and drill time.

Wilcox, Brian↗