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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Method and apparatus for evaluating superconducting tunnel junction detector noise versus bias voltage

A technique for characterizing the noise behavior of a superconducting tunnel junction (STJ) detector as a function of its applied bias voltage Vb by stepping the STJ's bias voltage across a predetermined range and, at each applied bias, making multiple measurements of the detector's current, calculating their mean and their standard deviation from their mean, and using this standard deviation as a measure of the STJ detector's noise at that applied bias. Because the method is readily executed under computer control, it is particularly useful when large numbers of STJ detectors require biasing, as in STJ detector arrays In a preferred implementation, the STJ is measured under computer control by attaching it to a digital spectrometer comprising a digital x-ray processor (DXP) coupled to a preamplifier that can set the STJ's bias voltage Vb using a digital-to-analog converter (DAC) controlled by the DXP.

Warburton, William K.↗
DOE OSTI2020

Improving MPI Collective I/O for High Volume Non-Contiguous Requests With Intra-Node Aggregation

Two-phase I/O is a well-known strategy for implementing collective MPI-IO functions. It redistributes I/O requests among the calling processes into a form that minimizes the file access costs. As modern parallel computers continue to grow into the exascale era, the communication cost of such request redistribution can quickly overwhelm collective I/O performance. In this study, this effect has been observed from parallel jobs that run on multiple compute nodes with a high count of MPI processes on each node. Furthermore, to reduce the communication cost, we present a new design for collective I/O by adding an extra communication layer that performs request aggregation among processes within the same compute nodes. This approach can significantly reduce inter-node communication contention when redistributing the I/O requests. We evaluate the performance and compare it with the original two-phase I/O on Cray XC40 parallel computers (Theta and Cori) with Intel KNL and Haswell processors. Using I/O patterns from two large-scale production applications and an I/O benchmark, we show our proposed method effectively reduces the communication cost and hence maintains the scalability for a large number of processes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Modeling UV Radiation Feedback from Massive Stars. I. Implementation of Adaptive Ray-tracing Method and Tests [Modeling UV Radiation Feedback from Massive Stars: I. Implementation of Adaptive Ray Tracing Algorithm]

Here, we present an implementation of an adaptive ray-tracing (ART) module in the Athena hydrodynamics code that accurately and efficiently handles the radiative transfer involving multiple point sources on a three-dimensional Cartesian grid. We adopt a recently proposed parallel algorithm that uses nonblocking, asynchronous MPI communications to accelerate transport of rays across the computational domain. We validate our implementation through several standard test problems, including the propagation of radiation in vacuum and the expansions of various types of H II regions. Additionally, scaling tests show that the cost of a full ray trace per source remains comparable to that of the hydrodynamics update on up to $\sim {10}^{3}$ processors. To demonstrate application of our ART implementation, we perform a simulation of star cluster formation in a marginally bound, turbulent cloud, finding that its star formation efficiency is 12% when both radiation pressure forces and photoionization by UV radiation are treated. We directly compare the radiation forces computed from the ART scheme with those from the M 1 closure relation. Although the ART and M 1 schemes yield similar results on large scales, the latter is unable to resolve the radiation field accurately near individual point sources.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2023

Recent advances in describing and driving crystal nucleation using machine learning and artificial intelligence

With the advent of faster computer processors and especially graphics processing units (GPUs) over the last few decades, the use of data-intensive machine learning (ML) and artificial intelligence (AI) has increased greatly, and the study of crystal nucleation has been one of the beneficiaries. In this study, we outline how ML and AI have been applied to address four outstanding difficulties of crystal nucleation: how to discover better reaction coordinates (RCs) for describing accurately non-classical nucleation situations; the development of more accurate force fields for describing the nucleation of multiple polymorphs or phases for a single system; more robust identification methods for determining crystal phases and structures; and as a method to yield improved course-grained models for studying nucleation.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2017

DIissolution of low enriched uranium from the experimental breeder reactor-II fuel stored at the Idaho National Laboratory

The Idaho National Laboratory (INL) is actively engaged in the development of electrochemical processing technology for the treatment of fast reactor fuels using irradiated fuel from the Experimental Breeder Reactor-II (EBR-II) as the primary test material. The research and development (R&D) activities generate a low enriched uranium (LEU) metal product from the electrorefining of the EBR-II fuel and the subsequent consolidation and removal of chloride salts by the cathode processor. The LEU metal ingots from past R&D activities are currently stored at INL awaiting disposition. One potential disposition pathway is the shipment of the ingots to the Savannah River Site (SRS) for dissolution in H-Canyon. Carbon steel cans containing the LEU metal would be loaded into reusable charging bundles in the H-Canyon Crane Maintenance Area and charged to the 6.4D or 6.1D dissolver. The LEU dissolution would be accomplished as the final charge in a dissolver batch (following the dissolution of multiple charges of spent nuclear fuel (SNF)). The solution would then be purified and the 235 U enrichment downblended to allow use of the U in commercial reactor fuel. To support this potential disposition path, the Savannah River National Laboratory (SRNL) developed a dissolution flowsheet for the LEU using samples of the material received from INL.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗
DOE OSTI2019

CTF 4.0 User's Manual

The deck version is specified using the PPV flag on Card 1.1. In general, you should always use the latest version of the CTF input deck in order to make sure your model is treated correctly in CTF. This feature was added to retain backwards compatibility for older input decks. When an input deck is created with the CTF pre-processor, the latest version will always be used. Table 1 provides the revision history of the CTF input deck. The first column gives the version number of the deck and the second columns gives a description of what changed since the previous version of the input deck. This document describes how to make a CTF input deck. A CTF input deck is organized into Card Groups and Cards. A Card Group is a collection of Cards. A Card is defined as a line of input. Each Card may contain multiple data. A Card is terminated by making a new line. This document has been organized so that each Card Group is discussed in its own dedicated chapter. Each card is discussed in its own dedicated section. Each data in the card is discussed in its own block. The block gives information about the data, including the number of the input, the title, a description of the meaning of the data, units, data type, and so on. An example block is shown below to discuss the meaning of each entry in the block.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC

Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. In addition, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkit (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011). Finally, our results suggest that variable cache line size can result in better performance and can also conserve power.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2016

Performance Models for Split-execution Computing Systems

Split-execution computing leverages the capabilities of multiple computational models to solve problems, but splitting program execution across different computational models incurs costs associated with the translation between domains. We analyze the performance of a split-execution computing system developed from conventional and quantum processing units (QPUs) by using behavioral models that track resource usage. We focus on asymmetric processing models built using conventional CPUs and a family of special-purpose QPUs that employ quantum computing principles. Our performance models account for the translation of a classical optimization problem into the physical representation required by the quantum processor while also accounting for hardware limitations and conventional processor speed and memory. We conclude that the bottleneck in this split-execution computing system lies at the quantum-classical interface and that the primary time cost is independent of quantum processor behavior.

multiprocessor↗
DOE OSTI2022

Numerical gate synthesis for quantum heuristics on bosonic quantum processors

There is a recent surge of interest and insights regarding the interplay of quantum optimal control and variational quantum algorithms. We study the framework in the context of qudits which are, for instance, definable as controllable electromagnetic modes of a superconducting cavity system coupled to a transmon. By employing recent quantum optimal control approaches described in (Petersson and Garcia, 2021), we showcase control of single-qudit operations up to eight states, and two-qutrit operations, mapped respectively onto a single mode and two modes of the resonator. We discuss the results of numerical pulse engineering on the closed system for parametrized gates useful to implement Quantum Approximate Optimization Algorithm (QAOA) for qudits. The results show that high fidelity ( > 0.99) is achievable with sufficient computational effort for most cases under study, and extensions to multiple modes and open, noisy systems are possible. The tailored pulses can be stored and used as calibrated primitives for a future compiler in circuit quantum electrodynamics (cQED) systems.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Refactoring the elastic–viscous–plastic solver from the sea ice model CICE v6.5.1 for improved performance

This study focuses on the performance of the elastic–viscous–plastic (EVP) dynamical solver within the sea ice model, CICE v6.5.1. The study has been conducted in two steps. First, the standard EVP solver was extracted from CICE for experiments with refactored versions, which are used for performance testing. Second, one refactored version was integrated and tested in the full CICE model to demonstrate that the new algorithms do not significantly impact the physical results. The study reveals two dominant bottlenecks, namely (1) the number of Message Parsing Interface (MPI) and Open Multi-Processing (OpenMP) synchronization points required for halo exchanges during each time step combined with the irregular domain of active sea ice points and (2) the lack of single-instruction, multiple-data (SIMD) code generation. The standard EVP solver has been refactored based on two generic patterns. The first pattern exposes how general finite differences on masked multi-dimensional arrays can be expressed in order to produce significantly better code generation by changing the memory access pattern from random access to direct access. The second pattern takes an alternative approach to handle static grid properties. The measured single-core performance improvement is more than a factor of 5 compared to the standard implementation. The refactored implementation of strong scales on the Intel® Xeon® Scalable Processors series node until the available bandwidth of the node is used. For the Intel® Xeon® CPU Max series, there is sufficient bandwidth to allow the strong scaling to continue for all the cores on the node, resulting in a single-node improvement factor of 35 over the standard implementation. This study also demonstrates improved performance on GPU processors.

58 GEOSCIENCES↗
DOE OSTI2017

CUDA Computation of the Feynman Distribution

In 2006, NVIDIA Corporation introduced the Computer Unified Device Architecture (CUDA) for C, C++, and Fortran programming languages. The CUDA parallel computing platform uses the Graphics Processing Unit (GPU) of NVIDIA graphics card, and it is designed for parallel computations. In these computations, the same algorithms are executed on the data in parallel. The GPU contains many Streaming Multiprocessors (SM) that can independently execute blocks of threads. A thread is a sequence of serial programmed instructions. The SM executes threads in groups of 32 and a group of 32 threads is called warp. The threads within a block can be synchronized and have access to a shared memory that is visible only to them. Conversely, blocks of threads cannot be synchronized and have access only to the global memory of the graphics card. This memory is called device memory and is independent of the host memory controlled by the Central Processing Unit (CPU). A single thread has access to a local memory (register) that is not visible to any other thread. The part of the program that is executed on the graphics card is called kernel. Each thread of the kernel has a unique identification index that is accessible by the in-built variable threadIdx; the latter is a 3-component vector. A threads block can contain up to 1024 threads. Blocks of threads have a unique identification index that is accessible by the in-built variable blockIdx; the latter is a 3-component vector. The in-built variable blockDim contains the number of threads per block; this variable is a 3-component vector. Threads and blocks represent different levels of parallelism; a kernel is executed as a grid of blocks of threads. Figure 1 illustrates a grid of thread blocks for a GPU with 2 SM. A SM can execute multiple blocks of threads in parallel; a block of threads is executed on a single SM. A GPU can execute multiple kernels concurrently. This work has used the Quadro M5000 graphics card with the following technical specifications: - 2048 cores with 861 MHz frequency, - 16 streaming multiprocessors, - 5.2 trillion transistors, - 8.2 Gb device memory, - 64 kb register memory (per thread), - 48 kb shared memory (per block) - 211.6 GB/s memory bandwidth, and - 3.5 GFLOPS floating point performance.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

High-performance computing with quantum processing units

The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into modern high-performance computing (HPC) systems. We examine how QPUs can be integrated into current and future HPC system architectures by accounting for func- tional and physical design requirements. We identify two integration pathways that are differentiated by infrastructure constraints on the QPU and the use cases expected for the HPC system. This includes a tight integration that assumes infrastructure bottlenecks can be overcome as well as a loose integration that as- sumes they cannot. We find that the performance of both approaches is likely to depend on the quantum interconnect that serves to entangle multiple QPUs. As a result, we also identify several challenges in assessing QPU performance for HPC, and we consider new metrics that capture the interplay between system architecture and the quantum parallelism underlying computational performance.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Parallel hybrid quantum-classical machine learning for kernelized time-series classification

Supervised time-series classification garners widespread interest because of its applicability throughout a broad application domain including finance, astronomy, biosensors, and many others. Here, in this work, we tackle this problem with hybrid quantum-classical machine learning, deducing pairwise temporal relationships between time-series instances using a timeseries Hamiltonian kernel (TSHK). A TSHK is constructed with a sum of inner products generated by quantum states evolved using a parameterized time evolution operator. This sum is then optimally weighted using techniques derived from multiple kernel learning. Because we treat the kernel weighting step as a differentiable convex optimization problem, our method can be regarded as an end-to-end learnable hybrid quantum-classical-convex neural network, or QCC-net, whose output is a data set-generalized kernel function suitable for use in any kernelized machine learning technique such as the support vector machine (SVM). Using our TSHK as input to a SVM, we classify univariate and multivariate time-series using quantum circuit simulators and demonstrate the efficient parallel deployment of the algorithm to 127-qubit superconducting quantum processors using quantum multi-programming.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

ML–Enabled FPGA Framework for Fast Quantum State Discrimination in Mid-Circuit Measurement Regimes

Accurate and low-latency quantum state discrimination is essential for protocols involving mid-circuit measurement (MCM) and conditional feed-forward. In superconducting quantum systems, conventional readout pipelines transfer measurement data to host processors for post-processing, introducing millisecond-scale delays that far exceed qubit coherence times. To overcome this bottleneck, we present an in-situ machine learning (ML) inference engine implemented on an FPGA for real-time quantum state discrimination. Our design performs inference directly on digitized readout signals with 40 ns latency, supports both qubit and qutrit readout, and enables conditional operations without host-side intervention. This capability is critical for MCM and for feedback-driven protocols such as quantum error correction. We validate the system on superconducting transmon hardware, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. We further demonstrate conditional qutrit logic driven by FPGA-resident classification, highlighting the potential of low-latency ML-on-FPGA control for NISQ applications and scalable fault-tolerant quantum computing.

Vora, Neel [Lawrence Berkeley National Laboratory ↗
DOE OSTI2021

EMPIRE-PIC: A Performance Portable Unstructured Particle-in-Cell Code

In this study we introduce EMPIRE-PIC, a finite element method particle-in-cell (FEM-PIC) application developed at Sandia National Laboratories. The code has been developed in C++ using the Trilinos library and the Kokkos Performance Portability Framework to enable running on multiple modern compute architectures while only requiring maintenance of a single codebase. EMPIRE-PIC is capable of solving both electrostatic and electromagnetic problems in two- and three-dimensions to second-order accuracy in space and time. In this paper we validate the code against three benchmark problems — a simple electron orbit, an electrostatic Langmuir wave, and a transverse electromagnetic wave propagating through a plasma. We demonstrate the performance of EMPIRE-PIC on four different architectures: Intel Haswell CPUs, Intel's Xeon Phi Knights Landing, ARM Thunder-X2 CPUs, and NVIDIA Tesla V100 GPUs attached to IBM POWER9 processors. This analysis demonstrates scalability of the code up to more than two thousand GPUs, and greater than one hundred thousand CPUs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Snowflake: A Lightweight Portable Stencil DSL

Stencil computations are not well optimized by general-purpose production compilers and the increased use of multicore, manycore, and accelerator-based systems makes the optimization problem even more challenging. In this paper we present Snowflake, a Domain Specific Language (DSL) for stencils that uses a 'micro-compiler' approach, i.e., small, focused, domain-specific code generators. The approach is similar to that used in image processing stencils, but Snowflake handles the much more complex stencils that arise in scientific computing, including complex boundary conditions, higher-order operators (larger stencils), higher dimensions, variable coefficients, non-unit-stride iteration spaces, and multiple input or output meshes. Snowflake is embedded in the Python language, allowing it to interoperate with popular scientific tools like SciPy and iPython; it also takes advantage of built-in Python libraries for powerful dependence analysis as part of a just-in-time compiler. We demonstrate the power of the Snowflake language and the micro-compiler approach with a complex scientific benchmark, HPGMG, that exercises the generality of stencil support in Snowflake. By generating OpenMP comparable to, and OpenCL within a factor of 2x of hand-optimized HPGMG, Snowflake demonstrates that a micro-compiler can support diverse processor architectures and is performance-competitive whilst preserving a high-level Python implementation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

MODAL FREQUENCY TRACKING: Performance Analysis on Noisy Experimental Ground Test Data

Mechanical devices operating in an environment contaminated by noise, uncertainties, and extraneous disturbances lead to low signal-to-noise-ratios creating an extremely challenging signal processing problem—especially for on-line, realtime, in-flight application. In this report, we discuss a model-based approach to incorporate physical device features into a dynamic structure that can be used to perform on-line tracking of modal frequencies. The approach we take, after pre-processing the raw measurement data, is to obtain a representation of the structural device under test that captures its underlying response to a suite of excitations and operating conditions. One approach is to apply modern system identification techniques based on stochastic subspace methods capable of both: (1) identifying the underlying black-box structure enabling the extraction of structural modes that can be used for analysis; and (2) modal tracking under continued vibrational excitation as in a real-time, in-flight like environment. The vibrational signature of the structural device is measured directly using a suite of tri-axial accelerometers characterizing a multiple input/multiple output (MIMO) dynamic system. In this analysis, we have 15 tri-axial accelerometer measurements or 45 total output channels along with a single excitation also measured with a tri-axial accelerometer providing a 3-input system for processing. We initially describe the experiment and then briefly develop the necessary background in stochastic subspace realization, discuss the algorithm and apply it to the isolated structural device, first, characterized by the set of noisy MIMO accelerometer measurements extracting the modal model from the data (subspace identification), extract the unique modal frequencies (modal coordinate transformation), track their evolution (real-time tracker) to evaluate the overall performance of the processor. Next we evaluate processor performance when the structural device is incorporated into a flight vehicle for further performance analysis. We summarize the results and predict performance.

42 ENGINEERING↗
DOE OSTI2024

Mode-multiplexed photonic integrated vector dot-product core from inverse design

Photonic computing has the potential to harness the full degrees of freedom (DOFs) of the light field, including the wavelength, spatial mode, spatial location, phase quadrature, and polarization, to achieve a higher level of computing parallelism and scalability than digital electronic processors. While multiplexing using the wavelength and other DOFs can be readily integrated on silicon photonics platforms with compact footprints, conventional mode-division multiplexed (MDM) photonic designs occupy areas exceeding tens to hundreds of microns for a few spatial modes, significantly limiting their scalability. Here, we utilize inverse design to demonstrate an ultracompact photonic computing core that calculates vector dot products based on MDM coherent mixing. Our dot-product core integrates the functionalities of two-mode multiplexers and one multimode coherent mixer within a nominal footprint of 5 μm x 3 μm . We have experimentally demonstrated computing examples on the fabricated dot-product core, including complex number multiplication and motion estimation using optical flow. The compact dot-product core design enables large-scale on-chip integration in a parallel photonic computing primitive cluster for high-throughput scientific computing and computer vision tasks.

97 MATHEMATICS AND COMPUTING↗