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This viewgraph presentation provides an overview of Field Programmable Gate Arrays (FPGAs), what they are, implementations in space missions, and current available technologies. Single Event Upsets (SEUs) and Single Event Transients (SETs) are discussed in relation to their effects on FPGAs. Testing goals, considerations, and data analysis are reviewed.
The infrared gas transducer used during extravehicular activity (EVA) in the extravehicular mobility unit (EMU) measures and reports the concentration of carbon dioxide (CO2) in the ventilation loop. It is nearing its end of life and there are a limited number remaining. Meanwhile, the next generation advanced portable life support system (PLSS) now being developed requires CO2 sensing technology with performance beyond that presently in use. A laser diode (LD) spectrometer based on wavelength modulation spectroscopy (WMS) is being developed to address both applications by Vista Photonics, Inc. Accommodation within space suits demands that optical sensors meet stringent size, weight, and power requirements. Version 1.0 devices were delivered to NASA Johnson Space Center (JSC) in 2011. The sensors incorporate a laser diode based CO2 channel that also includes an incidental water vapor (humidity) measurement. The prototypes are controlled digitally with a field-programmable gate array (FPGA)/microcontroller architecture. Version 2.0 devices with improved electronics and significantly reduced wetted volumes were delivered to JSC in 2012. A version 2.5 upgrade recently implemented wavelength stabilized operation, better humidity measurement, and much faster data analysis/reporting. A wholly reconfigured version 3.0 will maintain the demonstrated performance of earlier versions while being backwards compatible with the EMU and offering a radiation tolerant architecture.
Two-dimensional MEMS microshutter arrays (MSA) have been fabricated at the NASA Goddard Space Flight Center (GSFC) for the James Webb Space Telescope (JWST) to enable cryogenic (approximately 35 K) spectrographic astronomy measurements in the near-infrared region. Functioning as a focal plane object selection device, the MSA is a 2-D programmable aperture mask with fine resolution, high efficiency and high contrast. The MSA are close- packed silicon nitride shutters (cell size of 100 x 200 microns) patterned with a torsion flexure to allow opening to 90 degrees. A layer of magnetic material is deposited onto each shutter to permit magnetic actuation. Two electrodes are deposited, one onto each shutter and another onto the support structure side-wall, permitting electrostatic latching and 2-D addressing. New techniques were developed to test MSA under mission-similar conditions (8 K less than or equal to T less than 300K). The magnetic rotisserie has proven to be an excellent tool for rapid characterization of MSA. Tests conducted with the magnetic rotisserie method include accelerated cryogenic lifetesting of unpackaged 128 x 64 MSA and parallel measurement of the magneto-mechanical stiffness of shutters in pathfinder test samples containing multiple MSA designs. Lifetest results indicate a logarithmic failure rate out to approximately 10(exp 6) shutter actuations. These results have increased our understanding of failure mechanisms and provide a means to predict the overall reliability of MSA devices.
Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.
In industrial control systems (ICS), programmable logic controllers (PLC) are the embedded devices that directly control and monitor critical industrial infrastructure processes such as nuclear plants and power grid stations. Cyberattacks often target PLCs to sabotage a physical process. A memory forensic analysis of a suspect PLC can answer questions about an attack, including compromised firmware and manipulation of PLC control logic code and I/O devices. Given physical access to a PLC, collecting forensic information from the PLC memory at the hardware-level is risky and challenging. It may cause the PLC to crash or hang since PLCs have proprietary, legacy hardware with heterogeneous architecture. This paper addresses this research problem and proposes a novel JTAG (Joint Test Action Group)-based framework, Kyros, for reliable PLC memory acquisition. Kyros systematically creates a JTAG profile of a PLC through hardware assessment, JTAG pins identification, memory map creation, and optimizing acquisition parameters. It also facilitates the community of interest (such as ICS owners, operators, and vendors) to develop the JTAG profiles of PLCs. Further, we present a case study of Kyros implementation over Allen-Bradley 1756-A10/B to help understand the framework's application on a real-world PLC used in industry settings. The sample PLC memory dumps are shared with the research community to facilitate further research.
Secure environments face a steadily increasing threat from the introduction of scientific equipment that includes extensive software components. Devices such as powerful microscopes, 3d printers, programmable logic controllers, and many others, increase our capability and scientific output. Unfortunately, they now frequently include an entire computing stack with custom software bundled along with entire operating systems. Our ability to introspect and understand binary software is extremely limited, opening up the possibility of malicious third-parties including software that compromises our critical missions.
Introduction: Molecular communication is the transfer of information encoded by molecular structure and activity. We examine molecular communication within bacterial consortia as cells with diverse biosynthetic capabilities can be assembled for enhanced function. Their coordination, both in terms of engineered genetic circuits within individual cells as well as their population-scale functions, is needed to ensure robust performance. We have suggested that “electrogenetics,” the use of electronics to activate specific genetic circuits, is a means by which electronic devices can mediate molecular communication, ultimately enabling programmable control. Methods: Here, we have developed a graphical network model for dynamically assessing electronic and molecular signal propagation schemes wherein nodes represent individual cells, and their edges represent communication channels by which signaling molecules are transferred. We utilize graph properties such as edge dynamics and graph topology to interrogate the signaling dynamics of specific engineered bacterial consortia. Results: We were able to recapitulate previous experimental systems with our model. In addition, we found that networks with more distinct subpopulations (high network modularity) propagated signals more slowly than randomized networks, while strategic arrangement of subpopulations with respect to the inducer source (an electrode) can increase signal output and outperform otherwise homogeneous networks. Discussion: We developed this model to better understand our previous experimental results, but also to enable future designs wherein subpopulation composition, genetic circuits, and spatial configurations can be varied to tune performance. We suggest that this work may provide insight into the signaling which occurs in synthetically assembled systems as well as native microbial communities.
Instrument reduces manpower needed for testing electric powered vehicles. Device has dual scale that allows operator to compare actual speed with preprogrammed test speed. Features include large meter, buzzer, packaging to allow ready interchange of memories with different profiles, small size, minimal current drain, and reverse supply voltage protection.
This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.
Human Machine Interface (HMI) Programming and Testing is about creating graphical displays to mimic mission critical ground control systems in order to provide NASA engineers with the ability to monitor the health management of these systems in real time. The Health Management System (HMS) is an online interactive human machine interface system that monitors all Kennedy Ground Control Subsystem (KGCS) hardware in the field. The Health Management System is essential to NASA engineers because it allows remote control and monitoring of the health management systems of all the Programmable Logic Controllers (PLC) and associated field devices. KGCS will have equipment installed at the launch pad, Vehicle Assembly Building, Mobile Launcher, as well as the Multi-Purpose Processing Facility. I am designing graphical displays to monitor and control new modules that will be integrated into the HMS. The design of the display screen will closely mimic the appearance and functionality of the actual modules. There are many different field devices used to monitor health management and each device has its own unique set of health management related data, therefore each display must also have its own unique way to display this data. Once the displays are created, the RSLogix5000 application is used to write software that maps all the required data read from the hardware to the graphical display. Once this data is mapped to its corresponding display item, the graphical display and hardware device will be connected through the same network in order to test all possible scenarios and types of data the graphical display was designed to receive. Test Procedures will be written to thoroughly test out the displays and ensure that they are working correctly before being deployed to the field. Additionally, the Kennedy Ground Controls Subsystem's user manual will be updated to explain to the NASA engineers how to use the new module displays.
Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.
Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.
Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.
Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.
The Fast TracKer (FTK) is an ATLAS trigger upgrade built for full-event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The associative memory board (AMB) serial link processor and the auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the processing unit (PU), which finds tracks using hits from eight layers of the inner detector. The PU works in pipeline with the second stage board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and four SSBs are installed in a VME crate. The high power consumption of the AMB, AUX, and SSB (respectively, of about 250, 70, and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared with a common VME setup, the 8 FTK core crates will use ≈60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and eight SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.
Programmable Logic Controllers (PLCs) are used to control devices throughout the power system since they have fast control capabilities and can utilize multiple types of communication interfaces. Therefore, studying and mitigating their vulnerabilities to electromagnetic pulse is important for the reliability of PLC operations. Here, in this paper, an effective impedance measurement scheme is proposed and demonstrated for three PLCs to estimate their susceptibility to an electromagnetic pulse. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Then different parameters of the impedance measurement setup are explored. Based on the measured impedance, the equivalent circuit is established to calculate the response of the device when subjected to the electromagnetic pulse. The voltage and current responses of different interfaces are compared utilizing the developed pulsed Current Injection (CI) method. Finally, the impedance measurement scheme is verified through testing using three measuring instruments. And the CI simulation experiments reveal the characteristics and susceptibilities of different PLCs interfaces, indicating that some protection measures are required for the reliable operation of the PLC.
The evolution of highly miniaturized electronic and mechanical systems will be accompanied by new problems and issues regarding the radiation response of these systems in the space environment. In this paper we discuss some of the more prominent radiation problems brought about by miniaturization. For example, autonomous micro-spacecraft will require large amounts of high density memory, most likely in the form of stacked, multichip modules of DRAM's, that must tolerate the radiation environment. However, advanced DRAM's (16 to 256 Mbit) are quite susceptible to radiation, particularly single event effects, and even exhibit new radiation phenomena that were not a problem for older, less dense memory chips. Another important trend in micro-spacecraft electronics is toward the use of low-voltage microelectronic systems that consume less power. However, the reduction in operating voltage also caries with it an increased susceptibility to radiation. In the case of application specific integrated microcircuits (ASIM's), advanced devices of this type, such as high density field programmable gate arrays (FPGA's) exhibit new single event effects (SEE), such as single particle reprogramming of anti-fuse links. New advanced bipolar circuits have been shown recently to degrade more rapidly in the low dose rate space environment than in the typical laboratory total dose radiation test used to qualify such devices. Thus total dose testing of these parts is no longer an appropriately conservative measure to be used for hardness assurance. We also note that the functionality of micromechanical Si-based devices may be altered due to the radiation-induced deposition of charge in the oxide passivation layers.
Due to the limit in computing power arising from the Von Neumann bottleneck, computational devices are being developed that mimic neuro-biological processing in the brain by correlating the device characteristics with the synaptic weight of neurons. This platform combines ionic liquid gating and electrowetting for programmable placement/connectivity of the ionic liquid. In this platform, both short-term potentiation (STP) and long-term potentiation (LTP) are realized via electrostatic and electrochemical doping of the amorphous indium gallium zinc oxide (aIGZO), respectively, and pulsed bias measurements are demonstrated for lower power considerations. While compatible with resistive elements, we demonstrate a platform based on transitive amorphous indium gallium zinc oxide (aIGZO) pixel elements. Using a lithium based ionic liquid, we demonstrate both potentiation (decrease in device resistance) and depression (increase in device resistance), and propose a 2D platform array that would enable a much higher pixel count via Active Matrix electrowetting.