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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗
NASA NTRS2011

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗
NASA NTRS2014

Method for Providing Semiconductors Having Self-Aligned Ion Implant

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Neudeck, Philip G.↗
NASA NTRS1981

Study of the effects of impurities on the properties of silicon solar cell

The effect of defects across the back-surface-field junction on the performance of high efficiency and thin solar cells, using a developed-perimeter device model for the three-dimensional defects is investigated. Significant degradation of open-circuit voltage can occur even if there are only a few defects distributed in the bulk of the solar cell. Two features in the thickness dependences of the fill factor and efficiency in impurity-doped back-surface-field solar cells are discovered in the exact numerical solution which are associated with the high injection level effect in the base and not predicted by the low-level analytical theory. What are believed to be the most accurate recombination parameters at the Ti center to date are also given and a theory is developed which is capable of distinguishing an acceptor-like deep level from a donor-like deep level using the measured values of the thermal emission and capture cross sections.

Sah, C. T.↗
NASA NTRS1985

Overview of processing activities aimed at higher efficiencies and economical production

An overview of processing activities aimed at higher efficiencies and economical production were presented. Present focus is on low-cost process technology for higher-efficiency cells of up to 18% or higher. Process development concerns center on the use of less than optimum silicon sheet, the control of production yields, and making uniformly efficient large-area cells. High-efficiency cell factors that require process development are bulk material perfection, very shallow junction formation, front-surface passivation, and finely detailed metallization. Better bulk properties of the silicon sheet and the keeping of those qualities throughout large areas during cell processing are required so that minority carrier lifetimes are maintained and cell performance is not degraded by high doping levels. When very shallow junctions are formed, the process must be sensitive to metallizatin punch-through, series resisitance in the cell, and control of dopant leaching during surface passivation. There is a need to determine the sensitivity to processing by mathematical modeling and experimental activities.

Bickler, D. B.↗
NASA NTRS1972

Solid state image sensing arrays

The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.

Sadasiv, G.↗
NASA NTRS1984

Emitter formation in dendritic web silicon solar cells

The use of liquid dopants and liquid masks for p-n junction formation in dendritic web solar cells was investigated and found to be equivalent to the use of gaseous dopants and CVD SiO2 masks previously used. This results in a projected cost reduction of 0.02 1980$/Watt for a 25 MW/year production line, and makes possible junction formation processes having a higher throughput than more conventional processes. The effect of a low-energy (0.4 keV) hydrogen ion implant on dendritic web solar cells was also investigated. Such an implant was observed to improve Voc and Jsc substantially. Measurements of internal quantum efficiency suggest that it is the base of the cell, rather than the emitter, which benefits from the hydrogen implant. The diffusion length for electrons in the p-type base increased from 53 microns to 150 microns in one case, with dendritic web cell efficiency being boosted to 15.2 percent. The mechanism by which low-energy hydrogen ions can penetrate deeply into the silicon to effect the observed improvement is not known at this time.

Meier, D. L.↗
NASA NTRS1975

Summary of theoretical and experimental investigation of grating type, silicon photovoltaic cells

Theoretical and experimental aspects are summarized for single crystal, silicon photovoltaic devices made by forming a grating pattern of p/n junctions on the light receiving surface of the base crystal. Based on the general semiconductor equations, a mathematical description is presented for the photovoltaic properties of such grating-like structures in a two dimensional form. The resulting second order elliptical equation is solved by computer modeling to give solutions for various, reasonable, initial values of bulk resistivity, excess carrier concentration, and surface recombination velocity. The validity of the computer model is established by comparison with p/n devices produced by alloying an aluminum grating pattern into the surface of n-type silicon wafers. Current voltage characteristics and spectral response curves are presented for cells of this type constructed on wafers of different resistivities and orientations.

Chen, L. Y.↗
NASA NTRS1979

Process Development for Automated Solar Cell and Module Production. Task 4: Automated Array Assembly

A baseline sequence for the manufacture of solar cell modules was specified. Starting with silicon wafers, the process goes through damage etching, texture etching, junction formation, plasma edge etch, aluminum back surface field formation, and screen printed metallization to produce finished solar cells. The cells were then series connected on a ribbon and bonded into a finished glass tedlar module. A number of steps required additional developmental effort to verify technical and economic feasibility. These steps include texture etching, plasma edge etch, aluminum back surface field formation, array layup and interconnect, and module edge sealing and framing.

Source record↗
NASA NTRS1978

Induced junction solar cell and method of fabrication

An induced junction solar cell is fabricated on a p-type silicon substrate by first diffusing a grid of criss-crossed current collecting n+ stripes and thermally growing a thin SiO2 film, and then, using silicon-rich chemical vapor deposition (CVD), producing a layer of SiO2 having inherent defects, such as silicon interstices, which function as deep traps for spontaneous positive charges. Ion implantation increases the stable positive charge distribution for a greater inversion layer in the p-type silicon near the surface. After etching through the oxide to parallel collecting stripes, a pattern of metal is produced consisting of a set of contact stripes over the exposed collecting stripes and a diamond shaped pattern which functions as a current collection bus. Then the reverse side is metallized.

Maserjian, J.↗
NASA NTRS1986

Process research of non-Czochralski silicon material

Simultaneous diffusion of liquid precursors containing phosphorus and boron into dendritic web silicon to form solar cell structures was investigated. A simultaneous junction formation techniques was developed. It was determined that to produce high quality cells, an annealing cycle (nominal 800 C for 30 min) should follow the diffusion process to anneal quenched-in defects. Two ohm-cm n-base cells were fabricated with efficiencies greater than 15%. A cost analysis indicated that the simultansous diffusion process costs can be as low as 65% of the costs of the sequential diffusion process.

Campbell, R. B.↗
NASA NTRS2009

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗
NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗
NASA NTRS2010

Solar cell circuit and method for manufacturing solar cells

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Mardesich, Nick↗
NASA NTRS1985

Silicon MINP solar cells

The MINP solar cell concept refers to a cell structure designed to be a base region dominated device. Thus, it is desirable that recombination losses are reduced to the point that they occur only in the base region. The most unique feature of the MINP cell design is that a tunneling contact is utilized for the metallic contact on the front surface. The areas under the collector grid and bus bar are passivated by a thin oxide of tunneling thickness. Efforts must also be taken to minimize recombination at the surface between grid lines, at the junction periphery and within the emitter. Results of both theoretical and experimental studies of silicon MINP cells are given. Performance calculations are described which give expected efficiencies as a function of base resistivity and junction depth. Fabrication and characterization of cells are discussed which are based on 0.2 ohm-cm substrates, diffused emitters on the order of 0.15 to 0.20 microns deep, and with Mg MIS collector grids. A total area AM 1 efficiency of 16.8% was achieved. Detailed analyses of photocurrent and current loss mechanisms are presented and utilized to discuss future directions of research. Finally, results reported by other workers are discussed.

Olsen, L. C.↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗