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NASA NTRS2011

Imaging the Moon's Core with Seismology

Constraining the structure of the lunar core is necessary to improve our understanding of the present-day thermal structure of the interior and the history of a lunar dynamo, as well as the origin and thermal and compositional evolution of the Moon. We analyze Apollo deep moonquake seismograms using terrestrial array processing methods to search for the presence of reflected and converted energy from the lunar core. Although moonquake fault parameters are not constrained, we first explore a suite of theoretical focal spheres to verify that fault planes exist that can produce favorable core reflection amplitudes relative to direct up-going energy at the Apollo stations. Beginning with stacks of event seismograms from the known distribution of deep moonquake clusters, we apply a polarization filter to account for the effects of seismic scattering that (a) partitions energy away from expected components of ground motion, and (b) obscures all but the main P- and S-wave arrivals. The filtered traces are then shifted to the predicted arrival time of a core phase (e.g. PcP) and stacked to enhance subtle arrivals associated with the Moon s core. This combination of filtering and array processing is well suited for detecting deep lunar seismic reflections, since we do not expect scattered wave energy from near surface (or deeper) structure recorded at varying epicentral distances and stations from varying moonquakes at varying depths to stack coherently. Our results indicate the presence of a solid inner and fluid outer core, overlain by a partial-melt-containing boundary layer (Table 1). These layers are consistently observed among stacks from four classes of reflections: P-to-P, S-to-P, P-to-S, and S-to-S, and are consistent with current indirect geophysical estimates of core and deep mantle properties, including mass, moment of inertia, lunar laser ranging, and electromagnetic induction. Future refinements are expected following the successful launch of the GRAIL lunar orbiter and SELENE 2 lunar lander missions.

Weber, Renee C.↗

NASA NTRS2001

The Mountains of Io: Global and Geological Perspectives from Voyager and Galileo

To search for local and global scale geologic associations that may be related to the internal dynamics of Io, we have completed a global catalog of all mountains and volcanic centers. We have identified 115 mountain structures (covering approx. 3% of the surface) and 541 volcanic centers, including paterae (calderas and dark spots) and shield volcanoes. The average length of an Ionian mountain is 157 km, with the longest being 570 km. The mean height of Ionian mountains is 6.3 km, and the highest known mountain is Boosaule Montes (17.5 +/- 3 km). Five basic morphologic types of mountains have been identified; mesa, plateau peak, ridge, and massif. Very few mountains bear any physical similarity. to classic volcanic landforms, but many resemble flatiron mountains on Earth and are interpreted as tilted crustal blocks. This would be consistent with the hypothesis that most mountains are thrust blocks formed as a result of compressive stresses built up in the lower crust due to the global subsidence of volcanic layers as they are buried over time. More than one mechanism may be responsible for all Ionian mountains, however. The proximity of some mountains to paterae may indicate a direct link between some mountains and volcanism, although it is not always clear which came first. In contrast to earlier studies, a pronounced bimodal pattern is observed in the global distribution of both mountains and volcanic centers. The regions of highest areal densities of volcanic centers are near the sub- and anti-Jovian regions, but are offset roughly 90deg in longitude from the two, regions of greatest concentration of mountains. This anticorrelation may indicate the overprinting of a second stress field on the global compressive stresses due to subsidence. The bimodal distribution of volcanic centers and mountains is consistent with models of asthenospheric tidal heating and internal convection developed by Tackley et al.Over regions of mantle upwelling, compressive stresses in the lower crust induced by global subsidence might be reduced, encouraging volcanism and discouraging mountain building. In regions of mantle downwelling, these compressive stresses in the lower crust might be increased, discouraging volcanism and encouraging mountain building. Alternatively, the global pattern may be related to possible (but undocumented) nonsynchronous rotation of lo, which would produce two regions each of compression and extension in the crust. Evidence of layering and of mass wasting, including landslides, block sliding, debris aprons and downslope creep, on Ionian mountains suggests that the crust of Io is essentially a layered stack of partially consolidated volcanic lavas and plume deposits, becoming more consolidated with depth. The lower crust especially may also be ductily deformed, punctuated by volcanic intrusions and faulting at paterae, and broken into blocks, some of which have been uplifted to form mountains.

Schenk, Paul↗

NASA NTRS1990

Error recovery in shared memory multiprocessors using private caches

The problem of recovering from processor transient faults in shared memory multiprocesses systems is examined. A user-transparent checkpointing and recovery scheme using private caches is presented. Processes can recover from errors due to faulty processors by restarting from the checkpointed computation state. Implementation techniques using checkpoint identifiers and recovery stacks are examined as a means of reducing performance degradation in processor utilization during normal execution. This cache-based checkpointing technique prevents rollback propagation, provides rapid recovery, and can be integrated into standard cache coherence protocols. An analytical model is used to estimate the relative performance of the scheme during normal execution. Extensions to take error latency into account are presented.

Wu, Kun-Lung↗

NASA NTRS1991

High-power converters for space applications

Phase 1 was a concept definition effort to extend space-type dc/dc converter technology to the megawatt level with a weight of less than 0.1 kg/kW (220 lb./MW). Two system designs were evaluated in Phase 1. Each design operates from a 5 kV stacked fuel cell source and provides a voltage step-up to 100 kV at 10 A for charging capacitors (100 pps at a duty cycle of 17 min on, 17 min off). Both designs use an MCT-based, full-bridge inverter, gaseous hydrogen cooling, and crowbar fault protection. The GE-CRD system uses an advanced high-voltage transformer/rectifier filter is series with a resonant tank circuit, driven by an inverter operating at 20 to 50 kHz. Output voltage is controlled through frequency and phase shift control. Fast transient response and stability is ensured via optimal control. Super-resonant operation employing MCTs provides the advantages of lossless snubbing, no turn-on switching loss, use of medium-speed diodes, and intrinsic current limiting under load-fault conditions. Estimated weight of the GE-CRD system is 88 kg (1.5 cu ft.). Efficiency of 94.4 percent and total system loss is 55.711 kW operating at 1 MW load power. The Maxwell system is based on a resonance transformer approach using a cascade of five LC resonant sections at 100 kHz. The 5 kV bus is converted to a square wave, stepped-up to a 100 kV sine wave by the LC sections, rectified, and filtered. Output voltage is controlled with a special series regulator circuit. Estimated weight of the Maxwell system is 83.8 kg (4.0 cu ft.). Efficiency is 87.2 percent and total system loss is 146.411 kW operating at 1 MW load power.

Park, J. N.↗

NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗

NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗

NASA NTRS1993

The Application of Microtechnology to Spacecraft On-Board Computing(abstract)

In this report, we will survey recent advances in chip packaging and stacking techniques that allow miniature computers to be developed for space applications. Several orders of magnitude reduction in mass, volume, and power consumption are possible using these techniques. Moreover, performance improvements can be achieved by increasing the scale of multiprocessing. Most importantly, long-term survivability can potentially be improved by increasing the level of redundancy and fault tolerance.

microtechnology computers multiprocessing packagin↗

DOE OSTI2025

Bridging paradigms: Designing for HPC-Quantum convergence

Here, this paper presents a comprehensive software stack architecture for integrating quantum computing (QC) capabilities with High-Performance Computing (HPC) environments. While quantum computers show promise as specialized accelerators for scientific computing, their effective integration with classical HPC systems presents significant technical challenges. We propose a hardware-agnostic software framework that supports both current noisy intermediate-scale quantum devices and future fault-tolerant quantum computers, while maintaining compatibility with existing HPC workflows. The architecture includes a quantum gateway interface, standardized APIs for resource management, and robust scheduling mechanisms to handle both simultaneous and interleaved quantum–classical workloads. Key innovations include: (1) a unified resource management system that efficiently coordinates quantum and classical resources, (2) a flexible quantum programming interface that abstracts hardware-specific details, (3) A Quantum Platform Manager API that simplifies the integration of various quantum hardware systems, and (4) a comprehensive tool chain for quantum circuit optimization and execution. We demonstrate our architecture through implementation of quantum–classical algorithms, including the variational quantum linear solver, showcasing the framework’s ability to handle complex hybrid workflows while maximizing resource utilization. This work provides a foundational blueprint for integrating QC capabilities into existing HPC infrastructures, addressing critical challenges in resource management, job scheduling, and efficient data movement between classical and quantum resources.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Fractional Quantum Anomalous Hall Effect

The realization of the fractional quantum anomalous Hall effect (FQAHE) in a zero-field fractional Chern insulator is a new advancement in condensed matter physics, resulting from the interplay among strong correlations, topology, and spontaneous time-reversal symmetry breaking in lattice systems. In this review, we highlight the experimental and theoretical progress toward achieving FQAHE in two material platforms: twisted bilayer MoTe 2 and rhombohedral-stacked multilayer graphene. These systems host narrow topological bands with nontrivial Chern numbers, enabling interaction-driven fractionalized states analogous to the fractional quantum Hall effect, but without external magnetic fields. We discuss how spontaneous ferromagnetism, moiré lattice reconstruction, and band topological effects underpin the emergence of FQAHE in twisted MoTe 2 . We describe experimental discoveries of zero-field fractional Chern insulators in both transport and optical experiments, as well as signatures of composite Fermi liquids and higher-energy Chern band, which may shed light on engineering nonabelian states. In rhombohedral graphene/hexagonal boron nitride moiré superlattices, we review the recent observations of fractionally quantized Hall resistance, connections between FQAHE and extended quantum anomalous Hall phases, and the coexistence of superconductivity and FQAHE. Furthermore, these discoveries not only deepen our understanding of strongly correlated topological matter but also open new frontiers for exploring nonabelian anyons, fault-tolerant quantum computation, and topological opto-spintronics free of magnetic fields.

bilayer↗

NASA NTRS2013

Stacked Transformer for Driver Gain and Receive Signal Splitting

In a high-speed signal transmission system that uses transformer coupling, there is a need to provide increased transmitted signal strength without adding active components. This invention uses additional transformers to achieve the needed gain. The prior art uses stronger drivers (which require an IC redesign and a higher power supply voltage), or the addition of another active component (which can decrease reliability, increase power consumption, reduce the beneficial effect of serializer/deserializer preemphasis or deemphasis, and/or interfere with fault containment mechanisms), or uses a different transformer winding ratio (which requires redesign of the transformer and may not be feasible with high-speed signals that require a 1:1 winding ratio). This invention achieves the required gain by connecting the secondaries of multiple transformers in series. The primaries of these transformers are currently either connected in parallel or are connected to multiple drivers. There is also a need to split a receive signal to multiple destinations with minimal signal loss. Additional transformers can achieve the split. The prior art uses impedance-matching series resistors that cause a loss of signal. Instead of causing a loss, most instantiations of this invention would actually provide gain. Multiple transformers are used instead of multiple windings on a single transformer because multiple windings on the same transformer would require a redesign of the transformer, and may not be feasible with high-speed transformers that usually require a bifilar winding with a 1:1 ratio. This invention creates the split by connecting the primaries of multiple transformers in series. The secondary of each transformer is connected to one of the intended destinations without the use of impedance-matching series resistors.

Driscoll, Kevin R.↗

NASA NTRS2010

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗

NASA NTRSDate not supplied

Performance of a Regenerative Fuel Cell System for the Lunar Surface

Regenerative fuel cells (RFCs) are an attractive energy storage solution for lunar missions as a technology capable of providing a higher specific energy (i.e., W∙h/kg) than state-of-the-art packaged Li-ion battery systems. An RFC consists of the (1 & 2) electrochemical stacks (chemical to electrical energy conversion to supply electricity to an external load, i.e. the fuel cell reaction, and electrical to chemical energy conversion of supplied electrical power to dissociate water into hydrogen and oxygen gases, i.e. water electrolysis), (3) fluidic conditioning, (4) reactant storage, (5) avionics, (6) power management and distribution (PMAD), and (7) thermal management. NASA’s Glenn Research Center has designed, assembled, and tested a breadboard RFC sys-tem capable of operating autonomously for multiple simulated lunar day/night cycles in a laboratory environment. The system is comprised of a non-flow through proton exchange membrane (PEM) fuel cell stack and a liquid-anode feed PEM electrolyzer (EZ) stack designed to electrochemically compress the reactants at balanced pressures up to 12.4 MPa (1800 psia). The fluidic conditioning, avionics, PMAD, and thermal management sub-systems are largely comprised of commercial-off-the-shelf components for this system-level development effort. The hardware is controlled by a CubeSat space processor running an operational program based on core flight architecture that can control the RFC hardware autonomously through a state machine with fault monitoring. The testing results highlighted here were completed with the system in an open-loop configuration such that reactants generated through water electrolysis were vented while gas cylinders supplied fuel cell operation. The breadboard operated autonomously, but there were five unplanned transitions to a safe state that required a manual restart after reviewing the data, determining a root cause, and implementing a solution. Four of the transitions were caused by the thermal management subsystem and the fifth was caused by a water management control issue in the EZ sub-system. The RFC system operated for over 550 hours with the final cycle being slightly abbreviated due to reasons unrelated to system performance.

Kerrigan Cain↗

NASA NTRSDate not supplied

Performance of a Regenerative Fuel Cell System for the Lunar Surface

Kerrigan Cain↗

DOE OSTI2025

Exponential Backoff and Its Security Implications for Safety-Critical OT Protocols over TCP/IP Networks

The convergence of Operational Technology (OT) and Information Technology (IT) networks has become increasingly prevalent with the growth of Industrial Internet of Things (IIoT) applications. This shift, while enabling enhanced automation, remote monitoring, and data sharing, also introduces new challenges related to communication latency and cybersecurity. Oftentimes, legacy OT protocols were adapted to the TCP/IP stack without an extensive review of the ramifications to their robustness, performance, or safety objectives. To further accommodate the IT/OT convergence, protocol gateways were introduced to facilitate the migration from serial protocols to TCP/IP protocol stacks within modern IT/OT infrastructure. However, they often introduce additional vulnerabilities by exposing traditionally isolated protocols to external threats. This study investigates the security and reliability implications of migrating serial protocols to TCP/IP stacks and the impact of protocol gateways, utilizing two widely used OT protocols: Modbus TCP and DNP3. Our protocol analysis finds a significant safety-critical vulnerability resulting from this migration, and our subsequent tests clearly demonstrate its presence and impact. A multi-tiered testbed, consisting of both physical and emulated components, is used to evaluate protocol performance and the effects of device-specific implementation flaws. Through this analysis of specifications and behaviors during communication interruptions, we identify critical differences in fault handling and the impact on time-sensitive data delivery. The findings highlight how reliance on lower-level IT protocols can undermine OT system resilience, and they inform the development of mitigation strategies to enhance the robustness of industrial communication networks.

DNP3↗

DOE OSTI2026

A cryogenic muon tagging system based on kinetic inductance detectors for superconducting quantum processors

Ionizing radiation has emerged as a potential limiting factor for superconducting quantum processors, inducing quasiparticle bursts and correlated errors that challenge fault-tolerant operation. Atmospheric muons are particularly problematic due to their high energy and penetration power, making passive shielding ineffective. Therefore, monitoring the real-time muon flux is crucial to guide the development of alternative error-correction or mitigation strategies. We present the design, simulation, and first operation of a cryogenic muon-tagging system based on kinetic inductance detectors (KIDs), developed as a stand-alone cryogenic particle-tagging module for superconducting quantum processors. The system consists of two KIDs arranged in a vertical stack and operated at ∼20 mK. Monte Carlo simulations based on Geant4 guided the prototype design and provided reference expectations for muon-tagging efficiency and accidental coincidences due to ambient γ-rays. We observed a muon-induced coincidence rate among the top and bottom detectors of (192 ± 9) $\times\,10^{-3}$ events s$^{−1}$, in excellent agreement with the Monte Carlo prediction. The prototype achieves a muon-tagging efficiency of about 90% with negligible dead time. These results demonstrate the feasibility of operating a muon-tagging system at millikelvin temperatures and represent a key step toward the integration of cryogenic veto systems with multi-qubit chips to mitigate muon-induced errors.

Mariani, Ambra [INFN, Rome] (ORCID:000000028184857↗

NASA NTRS2010

Predicting Ares I Reaction Control System Performance by Utilizing Analysis Anchored with Development Test Data

The Ares I launch vehicle is an integral part of NASA s Constellation Program, providing a foundation for a new era of space access. The Ares I is designed to lift the Orion Crew Module and will enable humans to return to the Moon as well as explore Mars.1 The Ares I is comprised of two inline stages: a Space Shuttle-derived five-segment Solid Rocket Booster (SRB) First Stage (FS) and an Upper Stage (US) powered by a Saturn V-derived J-2X engine. A dedicated Roll Control System (RoCS) located on the connecting interstage provides roll control prior to FS separation. Induced yaw and pitch moments are handled by the SRB nozzle vectoring. The FS SRB operates for approximately two minutes after which the US separates from the vehicle and the US Reaction Control System (ReCS) continues to provide reaction control for the remainder of the mission. A representation of the Ares I launch vehicle in the stacked configuration and including the Orion Crew Exploration Vehicle (CEV) is shown in Figure 1. Each Reaction Control System (RCS) design incorporates a Gaseous Helium (GHe) pressurization system combined with a monopropellant Hydrazine (N2H4) propulsion system. Both systems have two diametrically opposed thruster modules. This architecture provides one failure tolerance for function and prevention of catastrophic hazards such as inadvertent thruster firing, bulk propellant leakage, and over-pressurization. The pressurization system on the RoCS includes two ambient pressure-referenced regulators on parallel strings in order to attain the required system level single Fault Tolerant (FT) design for function while the ReCS utilizes a blow-down approach. A single burst disk and relief valve assembly is also included on the RoCS to ensure single failure tolerance for must-not-occur catastrophic hazards. The Reaction Control Systems are designed to support simultaneously firing multiple thrusters as required

Stein, William B.↗

DOE OSTI2026

A Cryogenic Muon Tagging System Integrated with a Superconducting Qubit Device for Radiation-Induced Error Mitigation

Superconducting qubits are highly sensitive to ionizing radiation, which can induce correlated errors and limit scalable fault-tolerant quantum computing. In particular, cosmic-ray muons can deposit energy in the substrate, generating phonon bursts that break Cooper pairs and produce quasiparticles, leading to correlated decoherence events across multiple qubits. We present the development of a cryogenic muon tagging system based on Kinetic Inductance Detectors (KIDs) and its integration with superconducting quantum hardware. Originally developed within the ACE-SuperQ project and validated as a standalone detector, the system demonstrated a muon tagging efficiency of approximately 90% and excellent agreement with Monte Carlo simulations. Building on this validation, the tagging system has been integrated with a multi-qubit superconducting chip operated in a dilution refrigerator. The detector configuration consists of a multi-layer KID stack arranged above and below the quantum device, enabling time-coincident identification of muon-induced events within the same cryogenic environment. The integrated setup has been successfully commissioned, enabling simultaneous operation of the qubit chip and the muon tagging system. A first measurement campaign has been carried out, and preliminary data show time-correlated events between the muon tagging detectors and the qubit readout. A quantitative analysis of radiation-induced effects on qubit performance is currently ongoing. This work represents a step toward the implementation of event-level radiation tagging as a tool for characterizing and potentially mitigating correlated errors in superconducting quantum processors, while establishing a modular platform for future studies at the interface between particle physics and quantum information science.

Roy, Tanay [Fermilab] (ORCID:000000019442862X)↗

NASA NTRS2002

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗