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DOE OSTI2022

High Velocity, Low‐Voltage Collective In‐Plane Switching in (100) BaTiO 3 Thin Films

Abstract Ferroelectrics are being increasingly called upon for electronic devices in extreme environments. Device performance and energy efficiency is highly correlated to clock frequency, operational voltage, and resistive loss. To increase performance it is common to engineer ferroelectric domain structure with highly‐correlated electrical and elastic coupling that elicit fast and efficient collective switching. Designing domain structures with advantageous properties is difficult because the mechanisms involved in collective switching are poorly understood and difficult to investigate. Collective switching is a hierarchical process where the nano‐ and mesoscale responses control the macroscopic properties. Using chemical solution synthesis, epitaxially nearly‐relaxed (100) BaTiO 3 films are synthesized. Thermal strain induces a strongly‐correlated domain structure with alternating domains of polarization along the [010] and [001] in‐plane axes and 90° domain walls along the [011] or [01] directions. Simultaneous capacitance–voltage measurements and band‐excitation piezoresponse force microscopy revealed strong collective switching behavior. Using a deep convolutional autoencoder, hierarchical switching is automatically tracked and the switching pathway is identified. The collective switching velocities are calculated to be ≈500 cm s −1 at 5 V (7 kV cm −1 ), orders‐of‐magnitude faster than expected. These combinations of properties are promising for high‐speed tunable dielectrics and low‐voltage ferroelectric memories and logic.

36 MATERIALS SCIENCE↗

NASA NTRS2007

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗

NASA NTRS2006

Design of a Multi-Level/Analog Ferroelectric Memory Device

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗

NASA NTRS1995

Mechanical properties testing and results for thermal barrier coatings

Thermal Barrier Coatings (TBC's) provide a significant challenge in the evaluation of their mechanical properties in ways that provide data that is not specimen dependent. The paper reviews various developments of the principal author over the past several years for both plasma sprayed and physical vapor deposited (PVD) materials, as well as new data on the fatigue behavior of one material system. The test methods that have been employed address tensile and compressive modulus and ultimate strength, tensile and compressive fatigue strength, and interfacial strength. This testing is now underway. Property testing is especially difficult for TBC's owing to the limitation on fabrication thickness of the coating. Bending tests are not used as these tests do not provide sufficiently uniform states of strain for property evaluations. Test specimens with uniform states of axial stress have been devised for each material system. The results show that the material property results between various experimenters and experimental methods are not yet consistent. However, the results provide critical design data at a suitable level of accuracy for life prediction. The paper will review both tensile and compressive mechanical testing of uniaxial specimens showing property dependencies on material density and temperatures for both material systems. Successful test results for both tensile and compressive fatigue loadings will be given. The test data shows that the fatigue strength of the TBC's is highly stress dependent in both loading conditions and is likely to depend on stress range and not mean stress. The fatigue strength of the plasma sprayed TBC's appears to increase with elevated temperatures in a range of temperatures below the creep activation temperature for the materials. The plasma sprayed TBC materials have been confirmed to have cyclic hysteresis at all temperature levels down to room temperature. Limited failure analysis data for various specimens suggest that the failure modes are driven by normal geometric discontinuities in the TBC's.

Cruse, T. A.↗