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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS1993

Coordinated field study for CaPE: Analysis of energy and water budgets

The objectives of this hydrologic cycle study are to understand and model (1) surface energy and land-atmosphere water transfer processes, and (2) interactions between convective storms and surface energy fluxes. A surface energy budget measurement campaign was carried out by an interdisciplinary science team during the period July 8 - August 19, 1991 as part of the Convection and Precipitation/Electrification Experiment (CaPE) in the vicinity of Cape Canaveral, FL. Among the research themes associated with CaPE is the remote estimation of rainfall. Thus, in addition to surface radiation and energy budget measurements, surface mesonet, special radiosonde, precipitation, high-resolution satellite (SPOT) data, geosynchronous (GOES) and polar orbiting (DMSP SSM/I, OLS; NOAA AVHRR) satellite data, and high altitude airplane data (AMPR, MAMS, HIS) were collected. Initial quality control of the seven surface flux station data sets has begun. Ancillary data sets are being collected and assembled for analysis. Browsing of GOES and radar data has begun to classify days as disturbed/undisturbed to identify the larger scale forcing of the pre-convective environment, convection storms and precipitation. The science analysis plan has been finalized and tasks assigned to various investigators.

Goodman, Steven J.↗
NASA NTRS1995

The Linux operating system: An introduction

Linux is a Unix-like operating system for Intel 386/486/Pentium based IBM-PCs and compatibles. The kernel of this operating system was written from scratch by Linus Torvalds and, although copyrighted by the author, may be freely distributed. A world-wide group has collaborated in developing Linux on the Internet. Linux can run the powerful set of compilers and programming tools of the Free Software Foundation, and XFree86, a port of the X Window System from MIT. Most capabilities associated with high performance workstations, such as networking, shared file systems, electronic mail, TeX, LaTeX, etc. are freely available for Linux. It can thus transform cheap IBM-PC compatible machines into Unix workstations with considerable capabilities. The author explains how Linux may be obtained, installed and networked. He also describes some interesting applications for Linux that are freely available. The enormous consumer market for IBM-PC compatible machines continually drives down prices of CPU chips, memory, hard disks, CDROMs, etc. Linux can convert such machines into powerful workstations that can be used for teaching, research and software development. For professionals who use Unix based workstations at work, Linux permits virtually identical working environments on their personal home machines. For cost conscious educational institutions Linux can create world-class computing environments from cheap, easily maintained, PC clones. Finally, for university students, it provides an essentially cost-free path away from DOS into the world of Unix and X Windows.

Bokhari, Shahid H.↗
NASA NTRSDate not supplied

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

heterogeneous processing system↗
NASA NTRS2023

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

David K. Rutishauser↗
NASA NTRS2011

Using Spare Logic Resources To Create Dynamic Test Points

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

Katz, Richard↗
NASA NTRS1993

Wide-bandwidth high-resolution search for extraterrestrial intelligence

A third antenna was added to the system. It is a terrestrial low-gain feed, to act as a veto for local interference. The 3-chip design for a 4 megapoint complex FFT was reduced to finished working hardware. The 4-Megachannel circuit board contains 36 MByte of DRAM, 5 CPLDs, the three large FFT ASICs, and 74 ICs in all. The Austek FDP-based Spectrometer/Power Accumulator (SPA) has now been implemented as a 4-layer printed circuit. A PC interface board has been designed and together with its associated user interface and control software allows an IBM compatible computer to control the SPA board, and facilitates the transfer of spectra to the PC for display, processing, and storage. The Feature Recognizer Array cards receive the stream of modulus words from the 4M FFT cards, and forward a greatly thinned set of reports to the PC's in whose backplane they reside. In particular, a powerful ROM-based state-machine architecture has been adopted, and DRAM has been added to permit integration modes when tracking or reobserving source candidates. The general purpose (GP) array consists of twenty '486 PC class computers, each of which receives and processes the data from a feature extractor/correlator board set. The array performs a first analysis on the provided 'features' and then passes this information on to the workstation. The core workstation software is now written. That is, the communication channels between the user interface, the backend monitor program and the PC's have working software.

Horowitz, Paul↗
NASA NTRSDate not supplied

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗
NASA NTRSDate not supplied

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗
NASA NTRS2005

Harnessing the Power of the Sun

The Environmental Research Aircraft and Sensor Technology (ERAST) Alliance was created in 1994 and operated for 9 years as a NASA-sponsored coalition of 28 members from small companies, government, universities, and nonprofit organizations. ERAST s goal was to foster development of remotely piloted aircraft technology for scientific, humanitarian, and commercial purposes. Some of the aircraft in the ERAST Alliance were intended to fly unmanned at high altitudes for days at a time, and flying for such durations required alternative sources of power that did not add weight. The most successful solution for this type of sustained flight is the lightest solar energy. Photovoltaic cells convert sunlight directly into electricity. They are made of semi-conducting materials similar to those used in computer chips. When sunlight is absorbed, electrons are knocked loose from their atoms, allowing electricity to flow. Under the ERAST Alliance, two solar-powered technology demonstration aircraft, Pathfinder and Helios, were developed. Pathfinder is a lightweight, remotely piloted flying wing aircraft that demonstrated the technology of applying solar cells for long-duration, high-altitude flight. Solar arrays covering most of the upper wing surface provide power for the aircraft s electric motors, avionics, communications, and other electronic systems. Pathfinder also has a backup battery system that can provide power for between 2 and 5 hours to allow limited-duration flight after dark. It was designed, built, and operated by AeroVironment, Inc., of Monrovia, California. On September 11, 1995, Pathfinder reached an altitude of 50,500 feet, setting a new altitude record for solar-powered aircraft. The National Aeronautic Association presented the NASA-industry team with an award for 1 of the 10 Most Memorable Record Flights of 1995.

Source record↗
NASA NTRS2023

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As the space economy continues to expand through increasingly easy access to advanced and inexpensive technology, space missions themselves have become more ambitious with exploration targets growing ever distant while simultaneously requiring larger guidance and communication budgets. These conflicting desires of distance and control drive the need for advanced on-board intelligent decision making to reduce communication and control limitations by automating as many mission functions as possible in-situ. While the amount of research on such Artificial Intelligence and Machine Learning (AI/ML) software modules has grown exponentially, the capacity to experimentally validate such software modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available bleeding-edge computational platforms via what is programmatically referred to as the BrainStack on the TechEdSat (TES-n) flight series. This on-orbit computational platform provides an evaluation laboratory where advanced software experiments are pre-loaded into memory prior to launch, then executed as payloads during mission operations with results reported back and program tweaks or new training sets uploaded as needed. Processors selected as part of the BrainStack are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and, more recently, neuromorphic processors, in LEO operations. Neuromorphic processors are of particular interest due to their superior power efficiency over GPUs in intelligent automation applications. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on TES-13, January 13, 2022, and continues to operate in orbit despite no significant modifications to harden the processor against the space environment. The Intel Loihi Gen-1 on TES-13 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. The processor is packaged in the Kapoho Bay USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by an Intel Pentium single-board computer to handle scheduling of the software application payloads and communications with the satellite’s primary computer. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the continually evolving BrainStack in the upcoming three TES-n/NOW flights. The Kapoho Point unit will incorporate eight Loihi-2 processors, enabling neural networks of up to one million neurons and one billion synapsis. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space automation applications may be initially tested.

Artificial Intelligence↗
NASA NTRS2015

Laser Remote Sensing From ISS: CATS Cloud and Aerosol Level 2 Data Products (Heritage Edition)

The Cloud-Aerosol Transport System (CATS) instrument was developed at NASA's Goddard Space Flight Center (GSFC) and deployed to the International Space Station (ISS) on 10 January 2015. CATS is mounted on the Japanese Experiment Module's Exposed Facility (JEM_EF) and will provide near-continuous, altitude-resolved measurements of clouds and aerosols in the Earth's atmosphere. The CATS ISS orbit path provides a unique opportunity to capture the full diurnal cycle of cloud and aerosol development and transport, allowing for studies that are not possible with the lidar aboard the CALIPSO platform, which flies in the sun-synchronous A-Train orbit." " One of the primary science objectives of CATS is to continue the CALIPSO aerosol and cloud profile data record to provide continuity of lidar climate observations during the transition from CALIPSO to EarthCARE. To accomplish this, the CATS project at NASA's Goddard Space Flight Center (GSFC) and the CALIPSO project at NASA's Langley Research Center (LaRC) are closely collaborating to develop and deliver a full suite of CALIPSO-like level 2 data products that will be produced using the newly acquired CATS level 1B data whenever CATS is operating in science modes 1. The CALIPSO mission is now well into its ninth year of on-orbit operations, and has developed a robust set of mature and well-validated science algorithms to retrieve the spatial and optical properties of clouds and aerosols from multi-wavelength lidar backscatter signals. By leveraging both new and existing NASA technical resources, this joint effort by the CATS and CALIPSO teams will deliver validated lidar data sets to the user community at the earliest possible opportunity. The science community will have access to two sets of CATS Level 2 data products. The "Operational" data products will be produced by the GSFC CATS team utilizing the new instrument capabilities (e.g., multiple FOVs and 1064 nm depolarization), while the "Heritage" data products created using the existing CALIPSO algorithms and the CATS 532 nm channels and the total 1064 nm channel. " Below is the development of the CATS "Heritage" level 2 software and data along with some initial results with operational data."

Rodier, Sharon↗
NASA NTRS1993

Catalog of Apollo 17 rocks. Volume 1: Stations 2 and 3 (South Massif)

The Catalog of Apollo 17 Rocks is a set of volumes that characterize each of 334 individually numbered rock samples (79 larger than 100 g) in the Apollo 17 collection, showing what each sample is and what is known about it. Unconsolidated regolith samples are not included. The catalog is intended to be used by both researchers requiring sample allocations and a broad audience interested in Apollo 17 rocks. The volumes are arranged geographically, with separate volumes for the South Massif and Light Mantle, the North Massif, and two volumes for the mare plains. Within each volume, the samples are arranged in numerical order, closely corresponding with the sample collection stations. The present volume, for the South Massif and Light Mantle, describes the 55 individual rock fragments collected at Stations two, two-A, three, and LRV-five. Some were chipped from boulders, others collected as individual rocks, some by raking, and a few by picking from the soil in the processing laboratory. Information on sample collection, petrography, chemistry, stable and radiogenic isotopes, rock surface characteristics, physical properties, and curatorial processing is summarized and referenced as far as it is known up to early 1992. The intention has been to be comprehensive: to include all published studies of any kind that provide information on the sample, as well as some unpublished information. References which are primarily bulk interpretations of existing data or mere lists of samples are not generally included. Foreign language journals were not scrutinized, but little data appears to have been published only in such journals. We have attempted to be consistent in format across all of the volumes, and have used a common reference list that appears in all volumes. Where possible, ages based on Sr and Ar isotopes have been recalculated using the 'new' decay constants recommended by Steiger and Jager; however, in many of the reproduced diagrams the ages correspond with the 'old' decay constants. In this volume, mg' or Mg' = atomic Mg/(Mg +Fe).

Ryder, Graham↗
NASA NTRS2000

A Cost Effective System Design Approach for Critical Space Systems

NASA-JSC required an avionics platform capable of serving a wide range of applications in a cost-effective manner. In part, making the avionics platform cost effective means adhering to open standards and supporting the integration of COTS products with custom products. Inherently, operation in space requires low power, mass, and volume while retaining high performance, reconfigurability, scalability, and upgradability. The Universal Mini-Controller project is based on a modified PC/104-Plus architecture while maintaining full compatibility with standard COTS PC/104 products. The architecture consists of a library of building block modules, which can be mixed and matched to meet a specific application. A set of NASA developed core building blocks, processor card, analog input/output card, and a Mil-Std-1553 card, have been constructed to meet critical functions and unique interfaces. The design for the processor card is based on the PowerPC architecture. This architecture provides an excellent balance between power consumption and performance, and has an upgrade path to the forthcoming radiation hardened PowerPC processor. The processor card, which makes extensive use of surface mount technology, has a 166 MHz PowerPC 603e processor, 32 Mbytes of error detected and corrected RAM, 8 Mbytes of Flash, and I Mbytes of EPROM, on a single PC/104-Plus card. Similar densities have been achieved with the quad channel Mil-Std-1553 card and the analog input/output cards. The power management built into the processor and its peripheral chip allows the power and performance of the system to be adjusted to meet the requirements of the application, allowing another dimension to the flexibility of the Universal Mini-Controller. Unique mechanical packaging allows the Universal Mini-Controller to accommodate standard COTS and custom oversized PC/104-Plus cards. This mechanical packaging also provides thermal management via conductive cooling of COTS boards, which are typically designed for convection cooling methods.

Abbott, Larry Wayne↗
NASA NTRS2011

Principles, Techniques, and Applications of Tissue Microfluidics

The principle of tissue microfluidics and its resultant techniques has been applied to cell analysis. Building microfluidics to suit a particular tissue sample would allow the rapid, reliable, inexpensive, highly parallelized, selective extraction of chosen regions of tissue for purposes of further biochemical analysis. Furthermore, the applicability of the techniques ranges beyond the described pathology application. For example, they would also allow the posing and successful answering of new sets of questions in many areas of fundamental research. The proposed integration of microfluidic techniques and tissue slice samples is called tissue microfluidics because it molds the microfluidic architectures in accordance with each particular structure of each specific tissue sample. Thus, microfluidics can be built around the tissues, following the tissue structure, or alternatively, the microfluidics can be adapted to the specific geometry of particular tissues. By contrast, the traditional approach is that microfluidic devices are structured in accordance with engineering considerations, while the biological components in applied devices are forced to comply with these engineering presets. The proposed principles represent a paradigm shift in microfluidic technology in three important ways: Microfluidic devices are to be directly integrated with, onto, or around tissue samples, in contrast to the conventional method of off-chip sample extraction followed by sample insertion in microfluidic devices. Architectural and operational principles of microfluidic devices are to be subordinated to suit specific tissue structure and needs, in contrast to the conventional method of building devices according to fluidic function alone and without regard to tissue structure. Sample acquisition from tissue is to be performed on-chip and is to be integrated with the diagnostic measurement within the same device, in contrast to the conventional method of off-chip sample prep and subsequent insertion into a diagnostic device. A more advanced form of tissue integration with microfluidics is tissue encapsulation, wherein the sample is completely encapsulated within a microfluidic device, to allow for full surface access. The immediate applications of these approaches lie with diagnostics of tissue slices and biopsy samples e.g. for cancer but the approaches would also be very useful in comparative genomics and other areas of fundamental research involving heterogeneous tissue samples.

Wade, Lawrence A.↗
NASA NTRSDate not supplied

The Design of a Flexible, Interoperable Navigation Signal for Future Lunar Missions

The LunaNet Interoperability Specification (LNIS) is a set of standards currently under development by NASA, ESA, and JAXA, which define a common, interoperable set of services and interfaces for lunar communication and navigation. The LNIS includes specifications for the GNSS-like Augmented Forward Signal (AFS). The LANS (Lunar Augmented Navigation Service) will be comprised of Multiple LunaNet Service Provider (LNSP) nodes broadcasting the AFS, such as NASA’s LCRNS (Lunar Communications Relay and Navigation Systems), ESA’s Moonlight LCNS (Lunar Communication and Navigation Services) and the Japan LNSS (Lunar Navigation Satellite System). The LANS will provide a GNSS-like capability enabling orbiting and surface users in lunar space (such as Artemis) to estimate their position, velocity and time as described in Giordano et al., (2023). Initial capabilities will focus on providing service to the lunar South pole region. The specification of AFS defines two orthogonal signal components on a single carrier, with the in-phase component (AFS-I) being a lower-chip-rate data channel tailored for applications where low SWaP is critical (e.g., IoT devices or search and rescue), and the quadrature component (AFS-Q) being a high-chip-rate data-less pilot signal for high-precision, robust lunar navigation and positioning applications. An initial description of AFS was provided in the LNIS, (2023), and initial analysis results were shown in Dafesh, et al., (2024). In this work, we provide rationale for updates to the LNIS that define key aspects of the signal including the primary spreading code designs for the data and pilot channels, and a three-tiered overlay code approach for the pilot channel that provides flexible signal acquisition alternatives, rapid time dissemination and robust frame Sync. The paper also describes a robust data sync word that is designed to enable frame Sync. for low-SWaP receivers that only use the I channel, as well as a low-density parity check code (LDPC) data message encoding design and interleaving definition. The work further describes the impact of the updated AFS design in terms of improved acquisition performance, interference resistance, navigation message capabilities and rapid absolute time dissemination for users able to access clock and ephemeris data over an external network. The cross-correlation and synchronization performance of the AFS design is also compared to potential alternatives, further providing rationale for the final signal design configuration.

LANS↗
NASA NTRS2025

The Design of a Flexible, Interoperable Navigation Signal for Future Lunar Missions

The LunaNet Interoperability Specification (LNIS) is a set of standards currently under development by NASA, ESA, and JAXA, which define a common, interoperable set of services and interfaces for lunar communication and navigation. The LNIS includes specifications for the GNSS-like Augmented Forward Signal (AFS). The LANS (Lunar Augmented Navigation Service) will be comprised of Multiple LunaNet Service Provider (LNSP) nodes broadcasting the AFS, such as NASA’s LCRNS (Lunar Communications Relay and Navigation Systems), ESA’s Moonlight LCNS (Lunar Communication and Navigation Services) and the Japan LNSS (Lunar Navigation Satellite System). The LANS will provide a GNSS-like capability enabling orbiting and surface users in lunar space (such as Artemis) to estimate their position, velocity and time as described in Giordano et al., (2023). Initial capabilities will focus on providing service to the lunar South pole region. The specification of AFS defines two orthogonal signal components on a single carrier, with the in-phase component (AFS-I) being a lower-chip-rate data channel tailored for applications where low SWaP is critical (e.g., IoT devices or search and rescue), and the quadrature component (AFS-Q) being a high-chip-rate data-less pilot signal for high-precision, robust lunar navigation and positioning applications. An initial description of AFS was provided in the LNIS, (2023), and initial analysis results were shown in Dafesh, et al., (2024). In this work, we provide rationale for updates to the LNIS that define key aspects of the signal including the primary spreading code designs for the data and pilot channels, and a three-tiered overlay code approach for the pilot channel that provides flexible signal acquisition alternatives, rapid time dissemination and robust frame Sync. The paper also describes a robust data sync word that is designed to enable frame Sync. for low-SWaP receivers that only use the I channel, as well as a low-density parity check code (LDPC) data message encoding design and interleaving definition. The work further describes the impact of the updated AFS design in terms of improved acquisition performance, interference resistance, navigation message capabilities and rapid absolute time dissemination for users able to access clock and ephemeris data over an external network. The cross-correlation and synchronization performance of the AFS design is also compared to potential alternatives, further providing rationale for the final signal design configuration.

LunaNet↗
NASA NTRS1987

Optoelectronic analogs of self-programming neural nets - Architecture and methodologies for implementing fast stochastic learning by simulated annealing

Self-organization and learning is a distinctive feature of neural nets and processors that sets them apart from conventional approaches to signal processing. It leads to self-programmability which alleviates the problem of programming complexity in artificial neural nets. In this paper architectures for partitioning an optoelectronic analog of a neural net into distinct layers with prescribed interconnectivity pattern to enable stochastic learning by simulated annealing in the context of a Boltzmann machine are presented. Stochastic learning is of interest because of its relevance to the role of noise in biological neural nets. Practical considerations and methodologies for appreciably accelerating stochastic learning in such a multilayered net are described. These include the use of parallel optical computing of the global energy of the net, the use of fast nonvolatile programmable spatial light modulators to realize fast plasticity, optical generation of random number arrays, and an adaptive noisy thresholding scheme that also makes stochastic learning more biologically plausible. The findings reported predict optoelectronic chips that can be used in the realization of optical learning machines.

Farhat, Nabil H.↗
NASA NTRS2019

High-Performance Spaceflight Computing (HPSC) Middleware Overview

High Performance Spacecraft Computing (HPSC) is a joint project between the National Aeronautics and Space Administration (NASA) and Air Force Research Lab (AFRL) to develop a high-performance multi-core radiation hardened flight processor. HPSC offers a new flight computing architecture to meet the needs of NASA missions through 2030 and beyond. Providing on the order of 100X the computational capacity of current flight processors for the same amount of power, the multicore architecture of the HPSC processor, or "Chiplet" provides unprecedented flexibility in a flight computing system by enabling the operating point to be set dynamically, trading among needs for computational performance, energy management and fault tolerance. The HPSC Chiplet is being developed by Boeing under contract to NASA, and is expected to provide prototypes in 2021. The HPSC Chiplet prototypes will be delivered with an evaluation board, system emulators, comprehensive system software, and a software development kit. In addition to the vendor deliverables, the AFRL is funding the development of a flexible Middleware to be developed by NASA Jet Propulsion Laboratory and NASA Goddard Space Flight Center. The HPSC Middleware provides a suite of thirteen high level services to manage the compute, memory and I/O resources of this complex device.This presentation will provide an overview of the HPSC project, including a hardware overview, system software overview, Middleware overview, and mission use cases. The hardware overview will provide a look at the 8 core High Performance Processing Subsystem (HPPS), the Real Time Processing Subsystem (RTPS), the Chiplet Configuration Management Subsystem, on chip peripherals, and high speed I/O. The system software overview will introduce the boot loaders, operating systems, device drivers, and software development environment. The Middleware overview will provide insight into the high-level services that will be provided to help mission developers manage the many resources and configurations made possible with the Chiplet. Finally, the presentation will provide a brief look at the mission use cases that can be enabled with this next generation architecture.

middleware↗