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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS1971

The effects of radiation on the outer planets grand tour

A handbook is presented which was designed to accompany an oral presentation on the effects of radiation on the outer planets grand tour (OPGT). A summary of OPGT radiation environments expected from natural sources and the radioisotope thermoelectric generators and basic radiation effects and processes are reviewed, and ionization and displacement effects are examined. The presentation summarizes the effects of radiation on miscellaneous spacecraft materials and devices. The annealing and hardening of electronics are described. Special emphasis is placed on microcircuits. Mathematical modeling of circuits affected by radiation and radiation environmental testing are discussed. A review of means of evaluating the performance and correcting failures of irradiated devices is also presented.

Source record↗
NASA NTRS1988

Hardware proofs using EHDM and the RSRE verification methodology

Examined is a methodology for hardware verification developed by Royal Signals and Radar Establishment (RSRE) in the context of the SRI International's Enhanced Hierarchical Design Methodology (EHDM) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. This methodology is applied to a 6-bit counter problem and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are improving both the RSRE methodology and the EHDM system.

Butler, Ricky W.↗
NASA NTRS1991

Ultra low power CMOS technology

This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

Burr, J.↗
NASA NTRS1993

Detection of CMOS bridging faults using minimal stuck-at fault test sets

The performance of minimal stuck-at fault test sets at detecting bridging faults are evaluated. New functional models of circuit primitives are presented which allow accurate representation of bridging faults under switch-level simulation. The effectiveness of the patterns is evaluated using both voltage and current testing.

Ijaz, Nabeel↗
NASA NTRS1995

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Russinoff, David M.↗
NASA NTRS2017

The Impact of Harness Impedance on Hall Thruster Discharge Oscillations

Hall thrusters exhibit characteristic discharge voltage and current oscillations during steady-state operation. The lower frequency breathing-mode current oscillations are inherent to each thruster and could impact thruster operation and power processing unit (PPU) design. The design of the discharge output filter, in particular, the output capacitor is important because it supplies the high peak current oscillations that the thruster demands. However, space-rated, high-voltage capacitors are not readily available and can have significant mass and volume. So, it is important for a PPU designer to know what is the minimum amount of capacitance required to operate a thruster. Through Simulation Program with Integrated Circuit Emphasis modeling and electrical measurements on the Hall Effect Rocket with Magnetic Shielding thruster, it was shown that the harness impedance between the power supply and the thruster is the main contributor towards generating voltage ripple at the thruster. Also, increasing the size of the discharge filter capacitor, as previously implemented during thruster tests, does not reduce the voltage oscillations. The electrical characteristics of the electrical harness between the discharge supply and the thruster is crucial to system performance and could have a negative impact on performance, life and operation.

hollow cathodes↗
NASA NTRS2017

The Impact of Harness Impedance on Hall Thruster Discharge Oscillations

Hall thrusters exhibit characteristic discharge voltage and current oscillations during steady-state operation. The lower frequency breathing-mode current oscillations are inherent to each thruster and could impact thruster operation and power processing unit (PPU) design. The design of the discharge output filter, in particular, the output capacitor is important because it supplies the high peak current oscillations that the thruster demands. However, space-rated, high-voltage capacitors are not readily available and can have significant mass and volume. So, it is important for a PPU designer to know what is the minimum amount of capacitance required to operate a thruster. Through Simulation Program with Integrated Circuit Emphasis modeling and electrical measurements on the Hall Effect Rocket with Magnetic Shielding thruster, it was shown that the harness impedance between the power supply and the thruster is the main contributor towards generating voltage ripple at the thruster. Also, increasing the size of the discharge filter capacitor, as previously implemented during thruster tests, does not reduce the voltage oscillations. The electrical characteristics of the electrical harness between the discharge supply and the thruster is crucial to system performance and could have a negative impact on performance, life and operation.

ion engines↗
NASA NTRS2025

Design and Simulation of Greatly Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged 500 °C Operation

This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n-channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.

Silicon Carbide↗
NASA NTRS1991

Investigations of detail design issues for the high speed acoustic wind tunnel using a 60th scale model tunnel. Part 1: Tests with open circuits

This report summarizes the tests on the 1:60 scale model of the High Speed Acoustic Wind Tunnel (HSAWT) performed during the period of November 1989 to December 1990. Throughout the testing the tunnel was operated in the 'open circuit mode', that is when the airflow was induced by a powerful exhaust fan located outside the tunnel circuit. The tests were first performed with the closed test section and were subsequently repeated with the open test section. While operating with the open test section, a novel device, called the 'nozzle-diffuser,' was also tested in order to establish its usefulness of increasing pressure recovery in the first diffuser. The tests established the viability of the tunnel design. The flow distribution in each tunnel component was found acceptable and pressure recovery in the diffusers were found satisfactory. The diffusers appeared to operate without flow separation. All tests were performed at NASA LaRC.

Barna, P. Stephen↗
NASA NTRS1973

Low-high junction theory applied to solar cells

Recent use of alloying techniques for rear contact formation has yielded a new kind of silicon solar cell, the back surface field (BSF) cell, with abnormally high open circuit voltage and improved radiation resistance. Several analytical models for open circuit voltage based on the reverse saturation current are formulated to explain these observations. The zero SRV case of the conventional cell model, the drift field model, and the low-high junction (LHJ) model can predict the experimental trends. The LHJ model applies the theory of the low-high junction and is considered to reflect a more realistic view of cell fabrication. This model can predict the experimental trends observed for BSF cells. Detailed descriptions and derivations for the models are included. The correspondences between them are discussed. This modeling suggests that the meaning of minority carrier diffusion length measured in BSF cells be reexamined.

Godlewski, M. P.↗
NASA NTRS1998

Computational Investigation of Helical Traveling Wave Tube Transverse RF Field Forces

In a previous study using a fully three-dimensional (3D) helical slow-wave circuit cold- test model it was found, contrary to classical helical circuit analyses, that transverse FF electric fields have significant amplitudes compared with the longitudinal component. The RF fields obtained using this helical cold-test model have been scaled to correspond to those of an actual TWT. At the output of the tube, RF field forces reach 61%, 26% and 132% for radial, azimuthal and longitudinal components, respectively, compared to radial space charge forces indicating the importance of considering them in the design of electron beam focusing.

Kory, Carol L.↗
NASA NTRS2017

Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Neudeck, Philip G.↗
NASA NTRS2017

Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 degrees Celsius durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Neudeck, Philip G.↗
NASA NTRS1991

Damping of structural vibrations with piezoelectric materials and passive electrical networks

The possibility of dissipating mechanical energy with piezoelectric material shunted with passive electrical circuits is investigated. The effective mechanical impedance for the piezoelectric element shunted by an arbitrary circuit is derived. The shunted piezoelectric is shown to possess frequency dependent stiffness and loss factor which are also dependent on the shunting circuit. The generally shunted model is specialized for two shunting circuits: the case of a resistor alone and that of a resistor and inductor. For resistive shunting, the material properties exhibit frequency dependence similar to viscoelastic materials, but are much stiffer and more independent of temperature. Shunting with a resistor and inductor introduces an electrical resonance, which can be optimally tuned to structural resonances in a manner analogous to a mechanical vibration arsorber. Techniques for analyzing systems which incorporate these shunting cases are presented and applied to a cantilevered beam experiment. The experimental results for both the resistive and resonant shunting circuits validate the shunted piezoelectric damping models.

Hagood, N. W.↗
NASA NTRS1997

Accurate Cold-Test Model of Helical TWT Slow-Wave Circuits

Recently, a method has been established to accurately calculate cold-test data for helical slow-wave structures using the three-dimensional electromagnetic computer code, MAFIA. Cold-test parameters have been calculated for several helical traveling-wave tube (TWT) slow-wave circuits possessing various support rod configurations, and results are presented here showing excellent agreement with experiment. The helical models include tape thickness, dielectric support shapes and material properties consistent with the actual circuits. The cold-test data from this helical model can be used as input into large-signal helical TWT interaction codes making it possible, for the first time, to design a complete TWT via computer simulation.

Kory, Carol L.↗