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At least 199 records · Page 11

Four-Cylinder Stirling-Engine Computer Program

Computer program developed for simulating steady-state and transient performance of four-cylinder Stirling engine. In model, four cylinders interconnected by four working spaces. Each working space contains seven volumes: one for expansion space, heater, cooler, and compression space and three for regenerator. Thermal time constant for regenerator mass associated with each regenator gas volume. Former code generates results very quickly, since it has only 14 state variables with no energy equation. Current code then used to study various aspects of Stirling engine in much more detail. Program written in FORTRAN IV for use on IBM 370 computer.

Daniele, C. J.↗

Fatigue and Damage Tolerance Analysis of a Hybrid Composite Tapered Flexbeam

The behavior of nonlinear tapered composite flexbeams under combined axial tension and cyclic bending loading was studied using coupon test specimens and finite element (FE) analyses. The flexbeams used a hybrid material system of graphite/epoxy and glass/epoxy and had internal dropped plies, dropped in an overlapping stepwise pattern. Two material configurations, differing only in the use of glass or graphite plies in the continuous plies near the midplane, were studied. Test specimens were cut from a full-size helicopter tail-rotor flexbeam and were tested in a hydraulic load frame under combined constant axialtension load and transverse cyclic bending loads. The first determination damage observed in the specimens occurred at the area around the tip of the outermost ply-drop group in the tapered region of the flexbeam, near the thick end. Delaminations grew slowly and stably, toward the thick end of the flexbeam, at the interfaces above and below the dropped-ply region. A 2D finite element model of the flexbeam was developed. The model was analyzed using a geometrically non-linear analysis with both the ANSYS and ABAQUS FE codes. The global responses of each analysis agreed well with the test results. The ANSYS model was used to calculate strain energy release rates (G) for delaminations initiating at two different ply-ending locations. The results showed that delaminations were more inclined to grow at the locations where they were observed in the test specimens. Both ANSYS and ABAQUS were used to calculate G values associated with delamination initiating at the observed location but growing in different interfaces, either above or below the ply-ending group toward the thick end, or toward the thin end from the tip of the resin pocket. The different analysis codes generated the same trends and comparable peak values, within 5-11 % for each delamination path. Both codes showed that delamination toward the thick region was largely mode II, and toward the thin region was predominantly mode I. The calculated peak G-values from either analysis predict delamination is most likely to occur along the same interface where it was observed in the test specimens. Calculated peak G values were used with material characterization data to calculate a curve relating the fatigue life of the specimens, N, to the applied transverse load, V, for a given constant axial load.

Murri, Gretchen B.↗

Verification of the ENDF/B-VII.1 Based MC 2 -3 Library Rev.1

The MC 2 -3 code, developed by Argonne National Laboratory under the DOE-NE NEAMS program, is a multigroup cross section generation code for fast reactor applications. Last year, the ENDF/B-VII.0 (E70) MC 2 -3 library, which has been extensively used, verified, and validated over a long period, was intensively reverified and updated to support the commercial grade dedication (CGD) requirement of the TerraPower Natrium project. This year, the ENDF/B-VII.1 (E71) MC 2 -3 library, the preliminary version of which was generated several years ago, was regenerated and rigorously verified to support the Natrium project as well as the completion of verification of the E71 library. The E71 library was verified using the process developed during the verification of the E70 library, including comparisons of cross sections with the NJOY-generated cross sections, comparisons of the resolved resonance cross sections with those using the PEDNF library, and comparison of total cross sections with the sum of partial cross sections. Additional verifications were conducted to ensure that the benchmark problem solutions with the E71 library are reasonable compared to the corresponding Monte Carlo solutions. Furthermore, the E71 gamma library was generated, which includes data for prompt gamma, delayed gamma, and delayed beta as well as neutron and gamma heating. The gamma library was verified at the level of individual isotopes. The EBR-II core solutions from MC 2 -3/ DIF3D and MCNP were compared, demonstrating that those solutions in terms of k-effective and assembly powers were in good agreement.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

Design approach for a microprocessor-based GPS time transfer receiver

The design concept and characteristics of a self-contained microprocessor-based Global Positioning System time transfer receiver is described. A prototype of this unit is currently in the test phase. It employs two-bit digital baseband correlation rather than analog IF correlation of the signals with the reference code. The correlator, numerically controlled oscillators and code generator are implemented in a special-purpose digital signal processor. The time is recovered in the digital code tracking loop, and final corrections are applied in the control processor. Other features of this design are: (1) drift-free digital mechanization; (2) high reliability of digital circuits; (3) flexible control capability of the microprocessor; and (4) potential for a high degree of digital VLSI chip development leading to compact, low-cost units.

Ould, P. C.↗

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗

Fiscal Year 2024 Software Quality Assurance Activities for the ARC Software

The continued goal of the ARC SQA project in the Advanced Reactor Technologies program of DOE is to resolve the QA gaps for the ARC software that limit, or prevent, commercialization of the software for industry users. This project started in earnest in fiscal year 2023 which saw the entire code system moved from a SVN repository to a GitLab repository and an associated software quality assurance plan (SQAP) developed and ratified. Most of the QA gaps in the ARC software were identified in collaboration with industry partners and work begin in fiscal year 2023 and continued in 2024. The primary documentation that is missing includes user manuals, user guides, software verification reports, and code coverage assessments. The SUMMAR manual was completed this fiscal year and work was started on creating manuals for SE2ANL, SE2RCT, and DASSH. Software verification work was carried out for DIF3D and REBUS in a previous program and the current fiscal year saw the completion of software verification reports for GAMSOR, GAMSRC, VARPOW, EvaluateFlux, and SUMMAR. The goal for the next fiscal year is to complete the PERSENT software verification work and begin planning the software verification work for DASSH, SE2ANL, and SE2RCT. The code coverage reports for DIF3D and MC2-3 were completed in the previous fiscal year and the goal is to generate code coverage reports for REBUS, GAMSOR, PERSENT, and DASSH in the coming fiscal year. A considerable amount of effort was spent in the current fiscal year working on the continuous integration capability for automated regression testing in GitLab. The first version of the testing was created in the previous fiscal year and applied to DIF3D and its utility programs. That testing was extended this year to cover GAMSOR, REBUS, and PERSENT. To accomplish this, the first version of the new testing methodology had to be updated to make a single output checking methodology viable for all of the ARC software. This will result in a single document to detail the automated regression testing methodology and minor documents to detail the tolerance settings that have been applied to the output for each ARC code. The previous methodology put into place with SVN would have required a separate document for each ARC code to detail the output checking methodology and the tolerance settings for the output from each code. Because some of our industry partners are providing funds to add new capabilities to the ARC software to meet their needs, all of which must be reviewed and approved by the SQA program funded by this project, a summary of that development work is detailed in this report. Overall progress on resolving the QA gaps has been good this year with the most impactful improvement for our industry partners in capability being the creation of a threaded version of DIF3D-VARIANT that allows the DIF3D, REBUS, and GAMSOR run times to be reduced by a factor of 4-6. The most impactful QA gap that was resolved was the software verification of GAMSRC and VARPOW.

97 MATHEMATICS AND COMPUTING↗

Calculation of two-dimensional inlet flow fields in a supersonic free stream: Program documentation and test cases

The use of a computer code for the calculation of two dimensional inlet flow fields in a supersonic free stream and a nonorthogonal mesh-generation code are illustrated by specific examples. Input, output, and program operation and use are given and explained for the case of supercritical inlet operation at a subdesign Mach number (M Mach free stream = 2.09) for an isentropic-compression, drooped-cowl inlet. Source listings of the computer codes are also provided.

Biringen, S. H.↗

Task 7: ADPAC User's Manual

The overall objective of this study was to develop a 3-D numerical analysis for compressor casing treatment flowfields. The current version of the computer code resulting from this study is referred to as ADPAC (Advanced Ducted Propfan Analysis Codes-Version 7). This report is intended to serve as a computer program user's manual for the ADPAC code developed under Tasks 6 and 7 of the NASA Contract. The ADPAC program is based on a flexible multiple- block grid discretization scheme permitting coupled 2-D/3-D mesh block solutions with application to a wide variety of geometries. Aerodynamic calculations are based on a four-stage Runge-Kutta time-marching finite volume solution technique with added numerical dissipation. Steady flow predictions are accelerated by a multigrid procedure. An iterative implicit algorithm is available for rapid time-dependent flow calculations, and an advanced two equation turbulence model is incorporated to predict complex turbulent flows. The consolidated code generated during this study is capable of executing in either a serial or parallel computing mode from a single source code. Numerous examples are given in the form of test cases to demonstrate the utility of this approach for predicting the aerodynamics of modem turbomachinery configurations.

Hall, E. J.↗

Automatic Synthesis of UML Designs from Requirements in an Iterative Process

The Unified Modeling Language (UML) is gaining wide popularity for the design of object-oriented systems. UML combines various object-oriented graphical design notations under one common framework. A major factor for the broad acceptance of UML is that it can be conveniently used in a highly iterative, Use Case (or scenario-based) process (although the process is not a part of UML). Here, the (pre-) requirements for the software are specified rather informally as Use Cases and a set of scenarios. A scenario can be seen as an individual trace of a software artifact. Besides first sketches of a class diagram to illustrate the static system breakdown, scenarios are a favorite way of communication with the customer, because scenarios describe concrete interactions between entities and are thus easy to understand. Scenarios with a high level of detail are often expressed as sequence diagrams. Later in the design and implementation stage (elaboration and implementation phases), a design of the system's behavior is often developed as a set of statecharts. From there (and the full-fledged class diagram), actual code development is started. Current commercial UML tools support this phase by providing code generators for class diagrams and statecharts. In practice, it can be observed that the transition from requirements to design to code is a highly iterative process. In this talk, a set of algorithms is presented which perform reasonable synthesis and transformations between different UML notations (sequence diagrams, Object Constraint Language (OCL) constraints, statecharts). More specifically, we will discuss the following transformations: Statechart synthesis, introduction of hierarchy, consistency of modifications, and "design-debugging".

Schumann, Johann↗

A Timer for Synchronous Digital Systems

The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.

McKenney, Elizabeth↗

A High Performance Sparse Tensor Algebra Compiler in MLIR

Sparse tensor algebra is widely used in many applications, including scientific computing, machine learning, and data analytics. The performance of sparse tensor algebra kernels strongly depends on the intrinsic characteristics of the input tensors, hence many storage formats are designed for tensors to achieve optimal performance for particular applications/architectures, which makes it challenging to implement and optimize every tensor operation of interest on a given architecture. We propose a tensor algebra domain-specific language (DSL) and compiler framework to automatically generate kernels for mixed sparse-dense tensor algebra operations. The proposed DSL provides high-level programming abstractions that resemble the familiar Einstein notation to represent tensor algebra operations. The compiler introduces a new Sparse Tensor Algebra dialect built on top of LLVM's extensible MLIR compiler infrastructure for efficient code generation while covering a wide range of tensor storage formats. Our compiler also leverages input-dependent code optimization to enhance data locality for better performance. Our results show that the performance of automatically generated kernels outperforms the state-of-the-art sparse tensor algebra compiler, with up to 20.92x, 6.39x, and 13.9x performance improvement over state-of-the-art tensor algebra compilers, for parallel SpMV, SpMM, and TTM, respectively.

Tian, Ruiqin↗

Quantum error correction from complexity in Brownian SYK

We study the robustness of quantum error correction in a one-parameter ensemble of codes generated by the Brownian SYK model, where the parameter quantifies the encoding complexity. The robustness of error correction by a quantum code is upper bounded by the “mutual purity” of a certain entangled state between the code subspace and environment in the isometric extension of the error channel, where the mutual purity of a density matrix ρAB is the difference $\mathcal{F}$ p ($A : B$) ≡ $\mathrm{T}$r $p^{2}_{AB}$ - $\mathrm{T}$r $p^{2}_{A}$ $\mathrm{T}$r $p^{2}_{B}$. We show that when the encoding complexity is small, the mutual purity is O(1) for the erasure of a small number of qubits (i.e., the encoding is fragile). However, this quantity decays exponentially, becoming O(1/N) for O(log N) encoding complexity. Further, at polynomial encoding complexity, the mutual purity saturates to a plateau of O(e -N ). We also find a hierarchy of complexity scales associated to a tower of subleading contributions to the mutual purity that quantitatively, but not qualitatively, adjust our error correction bound as encoding complexity increases. In the AdS/CFT context, our results suggest that any portion of the entanglement wedge of a general boundary subregion A with sufficiently high encoding complexity is robustly protected against low-rank errors acting on A with no prior access to the encoding map. From the bulk point of view, we expect such bulk degrees of freedom to be causally inaccessible from the region A despite being encoded in it.

1/N expansion↗

KokkACC: Enhancing Kokkos with OpenACC

Template metaprogramming is gaining popularity as a high-level solution for achieving performance portability on heterogeneous computing resources. Kokkos is a representative approach that offers programmers high-level abstractions for generic programming while most of the device-specific code generation and optimizations are delegated to the compiler through template specializations. For this, Kokkos provides a set of device-specific code specializations in multiple back ends, such as CUDA and HIP. Unlike CUDA or HIP, OpenACC is a high-level and directive-based programming model. This descriptive model allows developers to insert hints (pragmas) into their code that help the compiler to parallelize the code. The compiler is responsible for the transformation of the code, which is completely transparent to the programmer. This paper presents an OpenACC back end for Kokkos: KokkACC. As an alternative to Kokkos’s existing device-specific back ends, KokkACC is a multi-architecture back end providing a high-productivity programming environment enabled by OpenACC’s high-level and descriptive programming model. Moreover, we have observed competitive performance; in some cases, KokkACC is faster (up to 9×) than NVIDIA’s CUDA back end and much faster than OpenMP’s GPU offloading back end. This work also includes implementation details and a detailed performance study conducted with a set of mini-benchmarks (AXPY and DOT product) and three mini-apps (LULESH, miniFE and SNAP, a LAMMPS proxy mini-app).

Valero Lara, Pedro↗

An Automatic Code Synthesizer

This paper describes the design and architecture fo an automatic code sysnthesizer we call the ACG. The input to the ACG is a list of facts that must hold for the generated code, along with domain-specific knowledge (design rules and patterns).

programming programming code programming productiv↗

Automatic finite element generators

The design and implementation of a software system for generating finite elements and related computations are described. Exact symbolic computational techniques are employed to derive strain-displacement matrices and element stiffness matrices. Methods for dealing with the excessive growth of symbolic expressions are discussed. Automatic FORTRAN code generation is described with emphasis on improving the efficiency of the resultant code.

Wang, P. S.↗

The DESI N -body simulation project – I. Testing the robustness of simulations for the DESI dark time survey

ABSTRACT Analysis of large galaxy surveys requires confidence in the robustness of numerical simulation methods. The simulations are used to construct mock galaxy catalogues to validate data analysis pipelines and identify potential systematics. We compare three N-body simulation codes, abacus, gadget-2, and swift, to investigate the regimes in which their results agree. We run N-body simulations at three different mass resolutions, 6.25 × 108, 2.11 × 109, and 5.00 × 109 h−1 M⊙, matching phases to reduce the noise within the comparisons. We find systematic errors in the halo clustering between different codes are smaller than the Dark Energy Spectroscopic Instrument (DESI) statistical error for $s\ \gt\ 20\ h^{-1}$ Mpc in the correlation function in redshift space. Through the resolution comparison we find that simulations run with a mass resolution of 2.1 × 109 h−1 M⊙ are sufficiently converged for systematic effects in the halo clustering to be smaller than the DESI statistical error at scales larger than $20\ h^{-1}$ Mpc. These findings show that the simulations are robust for extracting cosmological information from large scales which is the key goal of the DESI survey. Comparing matter power spectra, we find the codes agree to within 1 per cent for k ≤ 10 h Mpc−1. We also run a comparison of three initial condition generation codes and find good agreement. In addition, we include a quasi-N-body code, FastPM, since we plan use it for certain DESI analyses. The impact of the halo definition and galaxy–halo relation will be presented in a follow-up study.

79 ASTRONOMY AND ASTROPHYSICS↗

wa-hls4ml and lui-gnn: A benchmark and GNN-based surrogate model for hls4ml resource and latency estimation

As machine learning (ML) increasingly serves as a tool for addressing real-time challenges in scientific applications, the development of advanced tooling has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as model synthesis, are now becoming limiting factors in the rapid iteration of designs. To reduce these emerging constraints, multiple efforts are being launched toward designing an ML-based surrogate model that estimates resource usage of synthesized accelerator architectures. This model would reduce the design iteration time, especially when designing within a set of given hardware constraints. This approach shows considerable potential, but as it stands, the effort is early and would benefit from coordination and standardization to assist future work as it emerges. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of more than 100,000 fully connected neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. In addition to the resource utilization and latency data provided, the dataset includes generated artifacts and log files for many of the synthesized neural networks, in order to support future research in ML-based code generation. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, as well as the average performance across a subset of the dataset. We measure the performance of a given predictor model through multiple metrics, including $R^2$ score and SMAPE on regression tasks, as well as inference time to further characterize the estimator under test. Additionally, we introduce the latency/utilization inference graph neural network (lui-gnn), a surrogate model that uses a graph neural network to represent input architectures in the form of a directed graph. This graph representation allows for a diverse set of model architectures to all be effectively handled by a surrogate model. We present the architecture and performance of the model, as evaluated by the new proposed benchmark, including SMAPE, $R^2$ score, and inference times, and find that lui-gnn generally predicts latency and utilization for the 75\% quantile within several percent of the synthesized resources on the synthetic test dataset, indicating that this approach of estimating resource and latency via a surrogate models has promise and warrants further research.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

LibraryX: A Framework for Cross-Library-Call Optimization

Scientific applications utilize performance libraries as a software engineering concept: these libraries encapsulate important and well-understood (mathematical) operations, allow for reuse, and are implemented and tuned by experts. Domain scientists then implement complex algorithms based on these domainspecific libraries. While individual library calls are optimized, larger performance gains across sequences of calls—sometimes spanning multiple libraries—are often unrealized, forcing a trade-off between performance and implementation complexity.To overcome this issue, we propose LibraryX, an approach and a system that allows for cross-library-call optimization even when library calls stem from multiple performance libraries. LibraryX annotates library calls with semantic information and optimizes entire directed acyclic graphs (DAGs) of calls dynamically using the SPIRAL code generation system. We demonstrate its effectiveness across a range of memory bound workloads, achieving significant speedups on Nvidia, AMD, and Intel accelerators compared to code using native libraries without cross-call optimization.

Rao, Sanil [Carnegie Mellon University,Department ↗