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The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI.
We present the description of a processor which has been implemented to generate map products starting from C-band interferometric data. The first stage of the processor consists of the conventional interferometric SAR processing producing a Digital Elevation Model (DEMs) and a SAR brightness image in sensor coordinates.
The NASA/JPL AIRSAR Integrated Processor (AIP) is a multi-frequency polarimetric and interferometric SAR processor designed for better understanding of scattering from different types of Earth terrain.
Strongly correlated topological phases of matter are central to modern condensed matter physics and quantum information technology but often challenging to probe and control in material systems. The experimental difficulty of accessing these phases has motivated the use of engineered quantum platforms for simulation and manipulation of exotic topological states. Among these, the Laughlin state stands as a cornerstone for topological matter, embodying fractionalization, anyonic excitations, and incompressibility. Although its bosonic analogs have been realized on programmable quantum simulators, a genuine fermionic Laughlin state has yet to be demonstrated on a quantum processor. Here, we realize the ν = 1/3 fermionic Laughlin state on IonQ’s trapped-ion quantum computer using an efficient and scalable Hamiltonian variational ansatz with 369 two-qubit gates on a 16-qubit circuit. Employing symmetry-verification error mitigation, we extract key observables that characterize the Laughlin state, including correlation hole, bulk-edge correspondence, and topological entanglement entropy, with strong agreement to exact diagonalization benchmarks. This work demonstrates an end-to-end workflow to simulate material-intrinsic topological orders and provides a starting point to explore its dynamics and excitations on digital quantum processors.
Quantum computing with qudits is an emerging approach that exploits a larger, more connected computational space, providing advantages for many applications, including quantum simulation and quantum error correction. Nonetheless, qudits are typically afflicted by more complex errors and suffer greater noise sensitivity which renders their scaling difficult. In this work, we introduce techniques to tailor arbitrary qudit Markovian noise to stochastic Weyl–Heisenberg channels and mitigate noise that commutes with our Clifford and universal two-qudit gate in generic qudit circuits. We experimentally demonstrate these methods on a superconducting transmon qutrit processor, and benchmark their effectiveness for multipartite qutrit entanglement and random circuit sampling, obtaining up to 3× improvement in our results. To the best of our knowledge, this constitutes the first-ever error mitigation experiment performed on qutrits. Our work shows that despite the intrinsic complexity of manipulating higher-dimensional quantum systems, noise tailoring and error mitigation can significantly extend the computational reach of today’s qudit processors.
Ionizing radiation has emerged as a potential limiting factor for superconducting quantum processors, inducing quasiparticle bursts and correlated errors that challenge fault-tolerant operation. Atmospheric muons are particularly problematic due to their high energy and penetration power, making passive shielding ineffective. Therefore, monitoring the real-time muon flux is crucial to guide the development of alternative error-correction or mitigation strategies. We present the design, simulation, and first operation of a cryogenic muon-tagging system based on kinetic inductance detectors (KIDs), developed as a stand-alone cryogenic particle-tagging module for superconducting quantum processors. The system consists of two KIDs arranged in a vertical stack and operated at ∼20 mK. Monte Carlo simulations based on Geant4 guided the prototype design and provided reference expectations for muon-tagging efficiency and accidental coincidences due to ambient γ-rays. We observed a muon-induced coincidence rate among the top and bottom detectors of (192 ± 9) $\times\,10^{-3}$ events s$^{−1}$, in excellent agreement with the Monte Carlo prediction. The prototype achieves a muon-tagging efficiency of about 90% with negligible dead time. These results demonstrate the feasibility of operating a muon-tagging system at millikelvin temperatures and represent a key step toward the integration of cryogenic veto systems with multi-qubit chips to mitigate muon-induced errors.
Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled-𝑍 gates across all qubit pairs, with a benchmarked average fidelity of 96.00% ± 0.08% and best fidelity of 97.14% ± 0.07%, limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15% ± 0.24% and 75.18% ± 0.11%, respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity.
Atom-loss errors are a major limitation of current state-of-the-art neutral-atom quantum computers and pose a significant challenge for scalable systems. In a quantum processor with cesium atoms, we demonstrate proof-of-principle circuit-based conversion of this form of leakage error to erasure errors via leakage-detection units (LDUs), which nondestructively map information about the presence or absence of the qubit onto the state of an ancilla. We benchmark the performance of the LDU using a three-outcome low-loss state-detection method and find that the LDU detects atom-loss errors with approximately 93.4% accuracy, limited by technical imperfections of our apparatus. We further compile and execute a SWAP LDU, wherein the roles of the original data atom and ancilla atom are exchanged under the action of the LDU, providing “free refilling” of atoms in the case of atom loss. This circuit-based leakage-to-erasure error conversion is a critical component of a neutral-atom quantum processor where the quantum information may significantly outlive the lifetime of any individual atom in the quantum register. Finally, we demonstrate that LDUs may also be used to handle other forms of leakage errors where population moves to states outside of the computational subspace.
Quantum dynamics on curved spacetime has never been directly probed beyond the Newtonian limit. Although we can describe such dynamics theoretically, experiments would provide empirical evidence that quantum theory holds even in this extreme limit. The practical challenge is the minute spacetime curvature difference over the length scale of the typical extent of quantum effects. Here, we propose a quantum network of alkaline earth (like) atomic processors for constructing a distributed quantum state that is sensitive to the differential proper time between its constituent atomic processor nodes, implementing a quantum observable that is affected by post-Newtonian curved spacetime. Conceptually, we propose to delocalize one clock between three locations by encoding the presence or absence of a clock into the state of the local atoms. By separating three atomic nodes over approximately kilometer-scale elevation differences and distributing one clock between them via a 𝑊 state, we demonstrate that the curvature of spacetime is manifest in the interference of the three different proper times that give rise to three distinct beat notes in our nonlocal observable. We further demonstrate that 𝑁-atom entanglement within each node enhances the interrogation bandwidth by a factor of 𝑁. We discuss how our proposed system can probe new facets of fundamental physics, such as the linearity, unitarity, and probabilistic nature of quantum theory on curved spacetime. Our protocol combines several recent advances with neutral atom and trapped ions to realize a novel quantum probe of gravity uniquely enabled by quantum networks.
Continuously parameterized two-qubit gates are a key feature of state-of-the-art trapped-ion quantum processors, as they have favorable error scalings and show distinct improvements in circuit performance over more restricted maximally entangling gatesets. In this work, we provide a comprehensive and pedagogical discussion on how to practically implement these continuously parameterized Mølmer–Sørensen gates on the Quantum Scientific Computing Open User Testbed, a low-level trapped-ion processor. To generate the arbitrary entangling angles, θ, we simply scale the amplitude of light used to generate the entanglement. However, doing so requires careful consideration of amplifier saturation as well as the variable light shifts that result. As such, we describe a method to calibrate and cancel the dominant fourth-order effects, followed by a dynamic virtual phase advance during the gate to cancel any residual light shifts, and find a linear scaling between θ and the residual light shift. Once we have considered and calibrated these effects, we demonstrate performance improvement with decreasing θ. Finally, we describe nuances of hardware control to transform the XX-type interaction of the arbitrary-angle Mølmer–Sørensen gate into a phase-agnostic and crosstalk-mitigating ZZ interaction.
Data compressor processor concept envisions a simplified system for telemetry communications. It is simultaneously a zero-order processor and a floating aperture, a variable aperture, and a binary integer aperture with a decoded buffet fullness counter.
Pre-processor, post-processor, and multiple level substructuring routines for data management in support of NASTRAN finite element structural analysis of spacecraft
The antenna aspect system used on the Radio Astronomy Explorer B spacecraft is described. This system consists of two facsimile cameras, a data encoder, and a data processor. Emphasis is placed on the discussion of the data processor, which contains a data compressor and a source encoder. With this compression scheme a compression ratio of 8 is achieved on a typical line of camera data. These compressed data are then convolutionally encoded.
Processor is written in FORTRAN with minimal machine-dependent coding, allowing easy conversion to various digital computers. It eliminates 19 continuation-card limit of current namelist processors and permits unlimited number of variables to be read in a single namelist declaration.
A test program was conducted with duPont duplicating film type SR 112 and SCOLOR developer and Kodak duplicating film types 2430, 2422, and FE 2628 (SO-467) and MX-641 developer to determine sensitometric and image quality characteristics of these materials when used with a fultron spray processor. The test results show that the SCOLOR developer foams excessively in the fultron processor when used with or without the addition of an antifoaming agent. The Kodak type FE 2628 film with MX-641 chemistry had the longest linear Log E range at a 1.0 gamma. Sensitometric curves and granularity traces for all film process combinations tested are included.
The application of associative memory processor equipment to conventional host processors type systems is discussed. Efforts were made to demonstrate how such application relieves the task burden of conventional systems, and enhance system speed and efficiency. Data cover comparative theoretical performance analysis, demonstration of expanded growth capabilities, and demonstrations of actual hardware in simulated environment.
The impact of charge-coupled device (CCD) processors on future instrumentation was investigated. The CCD devices studied process sampled analog data and are referred to as OP-SAPS - operational sampled analog processors. Preliminary studies into various architectural configurations for systems composed of OP-SAPS show that they have potential in such diverse applications as pattern recognition and automatic control. It appears probable that OP-SAPS may be used to construct computing structures which can serve as special peripherals to large-scale computer complexes used in real time flight simulation. The research was limited to the following benchmark programs: (1) face recognition, (2) voice command and control, (3) terrain classification, and (4) terrain identification. A small amount of effort was spent on examining a method by which OP-SAPS may be used to decrease the limiting ground sampling distance encountered in remote sensing from satellites.
The MIDAS (Multivariate Interactive Digital Analysis System) processor is a high-speed processor designed to process multispectral scanner data (from Landsat, EOS, aircraft, etc.) quickly and cost-effectively to meet the requirements of users of remote sensor data, especially from very large areas. MIDAS consists of a fast multipipeline preprocessor and classifier, an interactive color display and color printer, and a medium scale computer system for analysis and control. The system is designed to process data having as many as 16 spectral bands per picture element at rates of 200,000 picture elements per second into as many as 17 classes using a maximum likelihood decision rule.