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The program, LACVIN, calculates vegetative indexes numbers on limited area coverage/high resolution picture transmission data for selected IJ grid sections. The IJ grid sections were previously extracted from the full resolution data tapes and stored on disk files.
The program, LACSEG, converts LAC/HRPT data tapes to the CSC defined Universal format. The Universal formatted data tape is then processed the normal way by the FAS IMDACS system.
An automatic test was developed to test the ability of the deep space station (DSS) command subsystem and exciter to generate and radiate, from the exciter, the correct idle bit sequence for a given flight project or to store and radiate received command data elements and files without alteration. This test, called the command system output bit verification test, is an extension of the command system performance test (SPT) and can be selected as an SPT option. The test compares the bit stream radiated from the DSS exciter with reference sequences generated by the SPT software program. The command subsystem and exciter are verified when the bit stream and reference sequences are identical. It is a key element of the acceptance testing conducted on the command processor assembly (CPA) operational program (DMC-0584-OP-G) prior to its transfer from development to operations.
The SPAR computer software system is a collection of processors that perform particular steps in the finite-element structural analysis procedure. The data generated by each processor are stored on a data base complex residing on an auxiliary storage device, and these data are then used by subsequent processors. The SPAR data handling utilities use routines to transfer data between the processors and the data base complex. A detailed description of the data base complex organization is presented. A discussion of how these SPAR data handling utilities are used in an application program to perform desired user functions is given with the steps necessary to convert an existing program to a SPAR processor by incorporating these utilities. Finally, a sample SPAR processor is included to illustrate the use of the data handling utilities.
The task of creating software to run on a distributed system brings with it many problems not encountered in a uni-processor environment. The designer, in addition to creating a solution to meet the functional requirements of the applicaiton, must determine how to distribute that functionality in order to meet the nonfunctional requirements such as performance and fault tolerance. In the traditional approach to building distributed software systems, decisions of how to partition the software must be made early in the design process so that a separate program can be written for each of the processors in the system. This design paradigm is extremely vulnerable to changes in the target hardware environment, as well as being sensitive to poor initial guesses about what distribution of functionality will satisfy the nonfunctional requirements. The paradigm is also weak in that no compiler has a complete view of the system. Many of the advantages of using a powerful language system are lost in a one-program-per-processor environment. Another approach to the development of distributed software systems, Honeywell's Distributed Ada program, is presented.
The current ISS Water Recovery System (WRS) reclaims water from crew urine, humidity condensate, and Sabatier product water. Urine is initially processed by the Urine Processor Assembly (UPA) which recovers 75% of the urine as distillate. The remainder of the water is present in the waste brine which is currently disposed of as trash on ISS. For future missions this additional water must be reclaimed due to the significant resupply penalty for missions beyond Low Earth Orbit (LEO). NASA has pursued various technology development programs for a brine processor in the past several years. This effort has culminated in a technology down-select to identify the optimum technology for future manned missions. The technology selection is based on various criteria, including mass, power, reliability, maintainability, and safety. Beginning in 2016 the selected technology will be transitioned to a flight hardware program for demonstration on ISS. This paper summarizes the technology selection process, the competing technologies, and the rationale for the technology selected for future manned missions.
The design, implementation, and performance of a two-dimensional time-accurate Navier-Stokes solver for the CM2 supercomputer are described. The program uses a single processor for each grid point. Two different time-stepping methods have so far been implemented: an explicit third-order Runge-Kutta method and an implicit approximation-factorization method. The CM2 results are checked against those of a mature well-vectorized Cray 2 program, both for correctness and performance. The code is found to be correct, and the performance in some cases is up to several times that of the Cray 2.
A Monte Carlo mission simulation program has been developed to optimize the solar electric propulsion (SEP) thrust subsystem configuration for an Encke comet rendezvous mission. This program examines several possible options for interconnecting power processors to the mercury ion thrusters in order to enhance mission reliability and to reduce SEP subsystem weight. The quantity of power processors and ion thrusters required to perform the mission successfully depends not only on the total required thrust, but also on the individual thruster and power processor performance and reliability. Based on these considerations, it was necessary to determine the quantity of the active power processors and ion thrusters required at any time and the means of providing redundancy. The results provide the basis for selecting an optimum SEP thrust subsystem for this mission and other missions.
The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.
The computer code for the trajectory processor of the HP-9825A High Fidelity Relative Motion Program is described in detail. The processor is a 12-degrees-of-freedom trajectory integrator which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. Coding standards and flow charts are given and the computational logic is discussed.
The very high speed integrated circuit (VHSIC) program offers NASA and its contractors assured availability of military specification embedded computer components and integrated computer aided design/computer aided engineering and software development support that result in low system life costs for data management systems on the space station and the Earth Observatory Satellite. Viewgraphs given review progress in both the Department of Defense VHSIC program and the NASA VHSIC related insertion development of a general purpose processor are presented.
The processing of raw data obtained by the solar vector magnetograph at NASA-Marshall requires extensive arithmetic operations on large arrays of real numbers. The objectives of this summer faculty fellowship study are to: (1) learn the programming language of the MicroMSP Array Processor and adapt some existing data reduction routines to exploit its capabilities; and (2) identify other applications and/or existing programs which lend themselves to array processor utilization which can be developed by undergraduate student programmers under the provisions of project JOVE.
In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.
The Transmission Control Protocol/ Internet protocol (TCP/IP) interface for the Satellite Orbit Analysis Program (SOAP) provides the means for the software to establish real-time interfaces with other software. Such interfaces can operate between two programs, either on the same computer or on different computers joined by a network. The SOAP TCP/IP module employs a client/server interface where SOAP is the server and other applications can be clients. Real-time interfaces between software offer a number of advantages over embedding all of the common functionality within a single program. One advantage is that they allow each program to divide the computation labor between processors or computers running the separate applications. Secondly, each program can be allowed to provide its own expertise domain with other programs able to use this expertise.
Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.
Placement, routing, and scheduling are essential tasks for near-optimal performance of programs for noisy quantum processors. Reliable execution of an arbitrary quantum circuit on current devices requires routing methods that overcome connectivity limitations while meeting data locality requirements. However, current devices also express highly variable noise levels in both the quantum gates and quantum registers. This requires any routing algorithm to be adaptive to both the circuit and the operating conditions. We demonstrate near-optimal routing methods of noisy quantum states that minimize the overall error of data movement while also limiting the computational complexity of routing decisions. We evaluate our methods against the noise characteristics of a 20-qubit superconducting quantum processor.
The problems involved, approach taken, and solution arrived at are described in a software study to design a high speed, real time symbiont for analog telemetry processing. The symbiont design is based on the need for transferring data from one I/O device to another without significant use of core space or central processor time. The queues, programmed wait states, and teletype commands incorporated in the symbiont design are discussed.
The LRC MASS was modified and updated to include logic for efficient analysis of space shuttle payload operations. All MASS computer models were reviewed for compatibility with, and applicability to, the shuttle sortie mission. The MASS modification efforts were concentrated on two computer programs, the general scheduling model (GSM) and one day model (ODM). A new computer program, the DAYLIB Tape Processor, was developed to update the link between the GSM and ODM. The resulting MASS is an operationally efficient analytical tool that will allow a rapid assessment of shuttle and shuttle payload operations.