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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Memory monitoring by animals and humans

The authors asked whether animals and humans would use similarly an uncertain response to escape indeterminate memories. Monkeys and humans performed serial probe recognition tasks that produced differential memory difficulty across serial positions (e.g., primacy and recency effects). Participants were given an escape option that let them avoid any trials they wished and receive a hint to the trial's answer. Across species, across tasks, and even across conspecifics with sharper or duller memories, monkeys and humans used the escape option selectively when more indeterminate memory traces were probed. Their pattern of escaping always mirrored the pattern of their primary memory performance across serial positions. Signal-detection analyses confirm the similarity of the animals' and humans' performances. Optimality analyses assess their efficiency. Several aspects of monkeys' performance suggest the cognitive sophistication of their decisions to escape.

NASA Discipline Space Human Factors↗
DOE OSTI2025

A copula-based rank histogram ensemble filter

Serial ensemble filters implement triangular probability transport maps to reduce high-dimensional inference problems to sequences of state-by-state univariate inference problems. The univariate inference problems are solved by sampling posterior probability densities obtained by combining constructed prior densities with observational likelihoods according to Bayes' rule. Many serial filters in the literature focus on representing the marginal posterior densities of each state. However, rigorously capturing the conditional dependencies between the different univariate inferences is crucial to correctly sampling multidimensional posteriors. This work proposes a new serial ensemble filter, called the copula rank histogram filter (CoRHF), that seeks to capture the conditional dependency structure between variables via empirical copula estimates; these estimates are used to rigorously implement the triangular (state-by-state univariate) Bayesian inference. The success of the CoRHF is demonstrated on two-dimensional examples and the Lorenz'63 problem. A practical extension to the high-dimensional setting is developed by localizing the empirical copula estimation, and is demonstrated on the Lorenz'96 problem.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1972

Optical modulator system

The fabrication, test, and delivery of an optical modulator system which will operate with a mode-locked Nd:YAG laser indicating at either 1.06 or 0.53 micrometers is discussed. The delivered hardware operates at data rates up to 400 Mbps and includes a 0.53 micrometer electrooptic modulator, a 1.06 micrometer electrooptic modulator with power supply and signal processing electronics with power supply. The modulators contain solid state drivers which accept digital signals with MECL logic levels, temperature controllers to maintain a stable thermal environment for the modulator crystals, and automatic electronic compensation to maximize the extinction ratio. The modulators use two lithium tantalate crystals cascaded in a double pass configuration. The signal processing electronics include encoding electronics which are capable of digitizing analog signals between the limit of + or - 0.75 volts at a maximum rate of 80 megasamples per second with 5 bit resolution. The digital samples are serialized and made available as a 400 Mbps serial NRZ data source for the modulators. A pseudorandom (PN) generator is also included in the signal processing electronics. This data source generates PN sequences with lengths between 31 bits and 32,767 bits in a serial NRZ format at rates up to 400 Mbps.

Brand, J.↗
NASA NTRS1979

The 10 to the 8th power bit solid state spacecraft data recorder

The results are summarized of a program to demonstrate the feasibility of Bubble Domain Memory Technology as a mass memory medium for spacecraft applications. The design, fabrication and test of a partially populated 10 to the 8th power Bit Data Recorder using 100 Kbit serial bubble memory chips is described. Design tradeoffs, design approach and performance are discussed. This effort resulted in a 10 to the 8th power bit recorder with a volume of 858.6 cu in and a weight of 47.2 pounds. The recorder is plug reconfigurable, having the capability of operating as one, two or four independent serial channel recorders or as a single sixteen bit byte parallel input recorder. Data rates up to 1.2 Mb/s in a serial mode and 2.4 Mb/s in a parallel mode may be supported. Fabrication and test of the recorder demonstrated the basic feasibility of Bubble Domain Memory technology for such applications. Test results indicate the need for improvement in memory element operating temperature range and detector performance.

Murray, G. W.↗
NASA NTRS1987

Reciprocating linear motor

A reciprocating linear motor is formed with a pair of ring-shaped permanent magnets having opposite radial polarizations, held axially apart by a nonmagnetic yoke, which serves as an axially displaceable armature assembly. A pair of annularly wound coils having axial lengths which differ from the axial lengths of the permanent magnets are serially coupled together in mutual opposition and positioned with an outer cylindrical core in axial symmetry about the armature assembly. One embodiment includes a second pair of annularly wound coils serially coupled together in mutual opposition and an inner cylindrical core positioned in axial symmetry inside the armature radially opposite to the first pair of coils. Application of a potential difference across a serial connection of the two pairs of coils creates a current flow perpendicular to the magnetic field created by the armature magnets, thereby causing limited linear displacement of the magnets relative to the coils.

Goldowsky, Michael P.↗
NASA NTRS1993

Parallel methods for dynamic simulation of multiple manipulator systems

In this paper, efficient dynamic simulation algorithms for a system of m manipulators, cooperating to manipulate a large load, are developed; their performance, using two possible forms of parallelism on a general-purpose parallel computer, is investigated. One form, temporal parallelism, is obtained with the use of parallel numerical integration methods. A speedup of 3.78 on four processors of CRAY Y-MP8 was achieved with a parallel four-point block predictor-corrector method for the simulation of a four manipulator system. These multi-point methods suffer from reduced accuracy, and when comparing these runs with a serial integration method, the speedup can be as low as 1.83 for simulations with the same accuracy. To regain the performance lost due to accuracy problems, a second form of parallelism is employed. Spatial parallelism allows most of the dynamics of each manipulator chain to be computed simultaneously. Used exclusively in the four processor case, this form of parallelism in conjunction with a serial integration method results in a speedup of 3.1 on four processors over the best serial method. In cases where there are either more processors available or fewer chains in the system, the multi-point parallel integration methods are still advantageous despite the reduced accuracy because both forms of parallelism can then combine to generate more parallel tasks and achieve greater effective speedups. This paper also includes results for these cases.

Mcmillan, Scott↗
NASA NTRS1994

Marshall Space Flight Center head development program

This report summarizes the results of the candidate head evaluation for the new long-life magnetic head per the SOW of Contract No. NAS8-39407, MSFC Head Development Program. The original program plans were to test a candidate head, fabricate a new head, then qualify the new head. These activities were scheduled to be carried out between March 1993 and March 1994. The program was halted after the evaluation of the candidate head by NAS8-39407 Amendment No. 4. MSFC has provided and authorized the use the MARS-2000 SRB QUAL Recorder PN 10400-0677-801 - Serial Number 200004 (Datatape PN 591000 - Serial Number 1004), Reproduce Amplifier Module (RAM) Datatape PN 533040 - Serial Number 2006, associated cables, and magnetic tape on special SRB/DFI tapered reels to Datatape for this program. All the testing that has been done for the candidate head evaluation was done at Datatape's facility in Pasadena,CA. The testing was performed in a Class 100,000 particle counts clean room at ambient temperature, except for the thermal testing which was conducted in a different area at Datatape. The Performance Verification Test Procedure PVT-11004-4 (PVT) and Acceptance Test Procedure ATP-11004-09 (ATP) procedures were used when tests were conducted on the recorder.

Harrer, Jim↗
NASA NTRS1995

A massively parallel computational approach to coupled thermoelastic/porous gas flow problems

A new computational scheme for coupled thermoelastic/porous gas flow problems is presented. Heat transfer, gas flow, and dynamic thermoelastic governing equations are expressed in fully explicit form, and solved on a massively parallel computer. The transpiration cooling problem is used as an example problem. The numerical solutions have been verified by comparison to available analytical solutions. Transient temperature, pressure, and stress distributions have been obtained. Small spatial oscillations in pressure and stress have been observed, which would be impractical to predict with previously available schemes. Comparisons between serial and massively parallel versions of the scheme have also been made. The results indicate that for small scale problems the serial and parallel versions use practically the same amount of CPU time. However, as the problem size increases the parallel version becomes more efficient than the serial version.

Shia, David↗
NASA NTRS1998

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Performance Verification Report: METSAT Phase Locked Oscillator Assembly, P/N 1334360-1, S/N's F03 and F04

Two Flight Model AMSU-A Phase Locked Oscillators (P/N 1348360-1, S/Ns F03 and F04) have been tested per AES Test Procedure AE-26758. The tests included vibration testing, thermal cycle testing, AM/FM Noise testing, and full functional testing. EMI/REO 2 Testing was not performed. (See test data for S/N F01). Both AMSU-A Phase Locked Oscillators satisfactorily passed all performance requirements of the AE-26633 Product specification. During thermal cycling of PLO serial number F03, the oven and data logger momentarily lost power, including a loss of data. The unit did not experience any thermal stress. TAR 003134 describes the corrective action. Prior to testing PLO serial number FO4, power was applied to the unit. (+15v,-15v) the unit did not display the proper phase lock. Upon test equipment check out a connector was found to be defective. TAR 003133 describes the corrective action. After completion of testing of PLO serial number F04 was installed into Receiver Assembly F02. Upon testing F02 Receiver Assembly the unit was found not to phase lock at ambient temperature. Removal of PLO Assembly F04 was required. R2 was the real issue. Solithane was secondary. Troubleshooting revealed excessive solithane on inner PLL Assembly cover inhibiting optimum grounding. Also, R2 was reselected which increased the lock range from -30 C to +60 C. TAR 002737 describes the corrective action.

Pines, D.↗
NASA NTRS1999

Performance and Application of Parallel OVERFLOW Codes on Distributed and Shared Memory Platforms

The presentation discusses recent studies on the performance of the two parallel versions of the aerodynamics CFD code, OVERFLOW_MPI and _MLP. Developed at NASA Ames, the serial version, OVERFLOW, is a multidimensional Navier-Stokes flow solver based on overset (Chimera) grid technology. The code has recently been parallelized in two ways. One is based on the explicit message-passing interface (MPI) across processors and uses the _MPI communication package. This approach is primarily suited for distributed memory systems and workstation clusters. The second, termed the multi-level parallel (MLP) method, is simple and uses shared memory for all communications. The _MLP code is suitable on distributed-shared memory systems. For both methods, the message passing takes place across the processors or processes at the advancement of each time step. This procedure is, in effect, the Chimera boundary conditions update, which is done in an explicit "Jacobi" style. In contrast, the update in the serial code is done in more of the "Gauss-Sidel" fashion. The programming efforts for the _MPI code is more complicated than for the _MLP code; the former requires modification of the outer and some inner shells of the serial code, whereas the latter focuses only on the outer shell of the code. The _MPI version offers a great deal of flexibility in distributing grid zones across a specified number of processors in order to achieve load balancing. The approach is capable of partitioning zones across multiple processors or sending each zone and/or cluster of several zones into a single processor. The message passing across the processors consists of Chimera boundary and/or an overlap of "halo" boundary points for each partitioned zone. The MLP version is a new coarse-grain parallel concept at the zonal and intra-zonal levels. A grouping strategy is used to distribute zones into several groups forming sub-processes which will run in parallel. The total volume of grid points in each group are approximately balanced. A proper number of threads are initially allocated to each group, and in subsequent iterations during the run-time, the number of threads are adjusted to achieve load balancing across the processes. Each process exploits the multitasking directives already established in Overflow.

Djomehri, M. Jahed↗
NASA NTRS2000

JavaGenes and Condor: Cycle-Scavenging Genetic Algorithms

A genetic algorithm code, JavaGenes, was written in Java and used to evolve pharmaceutical drug molecules and digital circuits. JavaGenes was run under the Condor cycle-scavenging batch system managing 100-170 desktop SGI workstations. Genetic algorithms mimic biological evolution by evolving solutions to problems using crossover and mutation. While most genetic algorithms evolve strings or trees, JavaGenes evolves graphs representing (currently) molecules and circuits. Java was chosen as the implementation language because the genetic algorithm requires random splitting and recombining of graphs, a complex data structure manipulation with ample opportunities for memory leaks, loose pointers, out-of-bound indices, and other hard to find bugs. Java garbage-collection memory management, lack of pointer arithmetic, and array-bounds index checking prevents these bugs from occurring, substantially reducing development time. While a run-time performance penalty must be paid, the only unacceptable performance we encountered was using standard Java serialization to checkpoint and restart the code. This was fixed by a two-day implementation of custom checkpointing. JavaGenes is minimally integrated with Condor; in other words, JavaGenes must do its own checkpointing and I/O redirection. A prototype Java-aware version of Condor was developed using standard Java serialization for checkpointing. For the prototype to be useful, standard Java serialization must be significantly optimized. JavaGenes is approximately 8700 lines of code and a few thousand JavaGenes jobs have been run. Most jobs ran for a few days. Results include proof that genetic algorithms can evolve directed and undirected graphs, development of a novel crossover operator for graphs, a paper in the journal Nanotechnology, and another paper in preparation.

Globus, Al↗
NASA NTRS2001

Method and Apparatus for High Data Rate Demodulation

A method to demodulate BPSK or QPSK data using clock rates for the receiver demodulator of one-fourth the data rate is presented. This is accomplished through multirate digital signal processing techniques. The data is sampled with an analog-to-digital converter and then converted from a serial data stream to a parallel data stream. This signal processing requires a clock cycle four times the data rate. Once converted into a parallel data stream, the demodulation operations including complex baseband mixing, lowpass filtering, detection filtering, symbol-timing recovery, and carrier recovery are all accomplished at a rate one-fourth the data rate. The clock cycle required is one-sixteenth that required by a traditional serial receiver based on straight convolution. The high rate data demodulator will demodulate BPSK, QPSK, UQPSK, and DQPSK with data rates ranging from 10 Mega-symbols to more than 300 Mega-symbols per second. This method requires less clock cycles per symbol tan traditional serial convolution techniques.

Gerald J Grebowsky↗
NASA NTRS2001

Code Parallelization with CAPO: A User Manual

A software tool has been developed to assist the parallelization of scientific codes. This tool, CAPO, extends an existing parallelization toolkit, CAPTools developed at the University of Greenwich, to generate OpenMP parallel codes for shared memory architectures. This is an interactive toolkit to transform a serial Fortran application code to an equivalent parallel version of the software - in a small fraction of the time normally required for a manual parallelization. We first discuss the way in which loop types are categorized and how efficient OpenMP directives can be defined and inserted into the existing code using the in-depth interprocedural analysis. The use of the toolkit on a number of application codes ranging from benchmark to real-world application codes is presented. This will demonstrate the great potential of using the toolkit to quickly parallelize serial programs as well as the good performance achievable on a large number of toolkit to quickly parallelize serial programs as well as the good performance achievable on a large number of processors. The second part of the document gives references to the parameters and the graphic user interface implemented in the toolkit. Finally a set of tutorials is included for hands-on experiences with this toolkit.

Jin, Hao-Qiang↗
NASA NTRS2006

Comparison of Communication Architectures for Spacecraft Modular Avionics Systems

This document is a survey of publicly available information concerning serial communication architectures used, or proposed to be used, in aeronautic and aerospace applications. It focuses on serial communication architectures that are suitable for low-latency or real-time communication between physically distributed nodes in a system. Candidates for the study have either extensive deployment in the field, or appear to be viable for near-term deployment. Eleven different serial communication architectures are considered, and a brief description of each is given with the salient features summarized in a table in appendix A. This survey is a product of the Propulsion High Impact Avionics Technology (PHIAT) Project at NASA Marshall Space Flight Center (MSFC). PHIAT was originally funded under the Next Generation Launch Technology (NGLT) Program to develop avionics technologies for control of next generation reusable rocket engines. After the announcement of the Space Exploration Initiative, the scope of the project was expanded to include vehicle systems control for human and robotics missions. As such, a section is included presenting the rationale used for selection of a time-triggered architecture for implementation of the avionics demonstration hardware developed by the project team

Gwaltney, D. A.↗
NASA NTRS2007

Circuit and Method for Communication Over DC Power Line

A circuit and method for transmitting and receiving on-off-keyed (OOK) signals with fractional signal-to-noise ratios uses available high-temperature silicon- on-insulator (SOI) components to move computational, sensing, and actuation abilities closer to high-temperature or high-ionizing radiation environments such as vehicle engine compartments, deep-hole drilling environments, industrial control and monitoring of processes like smelting, and operations near nuclear reactors and in space. This device allows for the networking of multiple, like nodes to each other and to a central processor. It can do this with nothing more than the already in-situ power wiring of the system. The device s microprocessor allows it to make intelligent decisions within the vehicle operational loop and to effect control outputs to its associated actuators. The figure illustrates how each node converts digital serial data to OOK 18-kHz in transmit mode and vice-versa in receive mode; though operations at lower frequencies or up to a megahertz are within reason using this method and these parts. This innovation s technique modulates a DC power bus with millivolt-level signals through a MOSFET (metal oxide semiconductor field effect transistor) and resistor by OOK. It receives and demodulates this signal from the DC power bus through capacitive coupling at high temperature and in high ionizing radiation environments. The demodulation of the OOK signal is accomplished by using an asynchronous quadrature detection technique realized by a quasi-discrete Fourier transform through use of the quadrature components (0 and 90 phases) of the carrier frequency as generated by the microcontroller and as a function of the selected crystal frequency driving its oscillator. The detected signal is rectified using an absolute-value circuit containing no diodes (diodes being non-operational at high temperatures), and only operational amplifiers. The absolute values of the two phases of the received signal are then summed and hard limited (digitized) by comparing them to a reference level and are then input into a microprocessor as a serial bit stream. The quasi-discrete Fourier transform is performed in high-temperature components (operational amplifiers, analog switches, resistors, and capacitors). The demodulated signal is a serial data stream that is input to the UART (universal asynchronous receiver transmitter) receiver pin of the microprocessor. The OOK of the carrier frequency uses the output of the UART pin as an enabling signal that drives the gate of the MOSFET. Logic low bits enable the carrier frequency (realized by using the 0 phase signal from the microcontroller, though either phase may be used) to be DC-coupled to the power supply bus through a current-limiting resistor mounted between the MOSFET drain and the supply rail. The presence of logic lows on the power supply rail is realized by carrier bursts while logic highs are realized by the absence of bursts.

Krasowski, Michael J.↗
NASA NTRS2010

Photon Counting Using Edge-Detection Algorithm

New applications such as high-datarate, photon-starved, free-space optical communications require photon counting at flux rates into gigaphoton-per-second regimes coupled with subnanosecond timing accuracy. Current single-photon detectors that are capable of handling such operating conditions are designed in an array format and produce output pulses that span multiple sample times. In order to discern one pulse from another and not to overcount the number of incoming photons, a detection algorithm must be applied to the sampled detector output pulses. As flux rates increase, the ability to implement such a detection algorithm becomes difficult within a digital processor that may reside within a field-programmable gate array (FPGA). Systems have been developed and implemented to both characterize gigahertz bandwidth single-photon detectors, as well as process photon count signals at rates into gigaphotons per second in order to implement communications links at SCPPM (serial concatenated pulse position modulation) encoded data rates exceeding 100 megabits per second with efficiencies greater than two bits per detected photon. A hardware edge-detection algorithm and corresponding signal combining and deserialization hardware were developed to meet these requirements at sample rates up to 10 GHz. The photon discriminator deserializer hardware board accepts four inputs, which allows for the ability to take inputs from a quadphoton counting detector, to support requirements for optical tracking with a reduced number of hardware components. The four inputs are hardware leading-edge detected independently. After leading-edge detection, the resultant samples are ORed together prior to deserialization. The deserialization is performed to reduce the rate at which data is passed to a digital signal processor, perhaps residing within an FPGA. The hardware implements four separate analog inputs that are connected through RF connectors. Each analog input is fed to a high-speed 1-bit comparator, which digitizes the input referenced to an adjustable threshold value. This results in four independent serial sample streams of binary 1s and 0s, which are ORed together at rates up to 10 GHz. This single serial stream is then deserialized by a factor of 16 to create 16 signal lines at a rate of 622.5 MHz or lower for input to a high-speed digital processor assembly. The new design and corresponding hardware can be employed with a quad-photon counting detector capable of handling photon rates on the order of multi-gigaphotons per second, whereas prior art was only capable of handling a single input at 1/4 the flux rate. Additionally, the hardware edge-detection algorithm has provided the ability to process 3-10 higher photon flux rates than previously possible by removing the limitation that photoncounting detector output pulses on multiple channels being ORed not overlap. Now, only the leading edges of the pulses are required to not overlap. This new photon counting digitizer hardware architecture supports a universal front end for an optical communications receiver operating at data rates from kilobits to over one gigabit per second to meet increased mission data volume requirements.

Gin, Jonathan W.↗
NASA NTRS2005

Portable Airborne Laser System Measures Forest-Canopy Height

(PALS) is a combination of laser ranging, video imaging, positioning, and data-processing subsystems designed for measuring the heights of forest canopies along linear transects from tens to thousands of kilometers long. Unlike prior laser ranging systems designed to serve the same purpose, the PALS is not restricted to use aboard a single aircraft of a specific type: the PALS fits into two large suitcases that can be carried to any convenient location, and the PALS can be installed in almost any local aircraft for hire, thereby making it possible to sample remote forests at relatively low cost. The initial cost and the cost of repairing the PALS are also lower because the PALS hardware consists mostly of commercial off-the-shelf (COTS) units that can easily be replaced in the field. The COTS units include a laser ranging transceiver, a charge-coupled-device camera that images the laser-illuminated targets, a differential Global Positioning System (dGPS) receiver capable of operation within the Wide Area Augmentation System, a video titler, a video cassette recorder (VCR), and a laptop computer equipped with two serial ports. The VCR and computer are powered by batteries; the other units are powered at 12 VDC from the 28-VDC aircraft power system via a low-pass filter and a voltage converter. The dGPS receiver feeds location and time data, at an update rate of 0.5 Hz, to the video titler and the computer. The laser ranging transceiver, operating at a sampling rate of 2 kHz, feeds its serial range and amplitude data stream to the computer. The analog video signal from the CCD camera is fed into the video titler wherein the signal is annotated with position and time information. The titler then forwards the annotated signal to the VCR for recording on 8-mm tapes. The dGPS and laser range and amplitude serial data streams are processed by software that displays the laser trace and the dGPS information as they are fed into the computer, subsamples the laser range and amplitude data, interleaves the subsampled data with the dGPS information, and records the resulting interleaved data stream.

Nelson, Ross↗
NASA NTRS2011

FPGA for Power Control of MSL Avionics

A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

Wang, Duo↗