Search NASA⌕ Search

SEARCH · Search NASA

Results for “ASIC”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

The Magnetospheric Multiscale Magnetometers

The success of the Magnetospheric Multiscale mission depends on the accurate measurement of the magnetic field on all four spacecraft. To ensure this success, two independently designed and built fluxgate magnetometers were developed, avoiding single-point failures. The magnetometers were dubbed the digital fluxgate (DFG), which uses an ASIC implementation and was supplied by the Space Research Institute of the Austrian Academy of Sciences and the analogue magnetometer (AFG) with a more traditional circuit board design supplied by the University of California, Los Angeles. A stringent magnetic cleanliness program was executed under the supervision of the Johns Hopkins University,s Applied Physics Laboratory. To achieve mission objectives, the calibration determined on the ground will be refined in space to ensure all eight magnetometers are precisely inter-calibrated. Near real-time data plays a key role in the transmission of high-resolution observations stored onboard so rapid processing of the low-resolution data is required. This article describes these instruments, the magnetic cleanliness program, and the instrument pre-launch calibrations, the planned in-flight calibration program, and the information flow that provides the data on the rapid time scale needed for mission success.

Magnetosphere↗
NASA NTRS2017

A Compact, Multi-view Net Flux Radiometer for Future Uranus and Neptune Probes

A Net Flux Radiometer (NFR) is presented that can be included in an atmospheric structure instrument suite for future probe missions to the icy giants Uranus and Neptune. The baseline design has two spectral channels i.e., a solar channel (0.4-to-3.5 m) and a thermal channel (4-to-300 m). The NFR is capable of viewing five distinct viewing angles during the descent. Non-imaging Winston cones with band-pass filters are used for each spectral channel and to define a 5 angular acceptance. Uncooled thermopile detectors are used in each spectral channel and are read out using a custom radiation hard application specific integrated circuit (ASIC). The baseline design can easily be changed to increase the number of detector channels from two to seven.

Aslam, S.↗
NASA NTRS2018

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

Design for reliability (DFR)↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRS2019

FPGA Mitigation Strategies for Critical Applications

Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being evaluated. They range from weak EDAC circuits that save area and power to strong mitigation strategies that are a great expense to systems. This presentation will focus on radiation induced susceptibilities for a variety of FPGA types and ASIC devices. In addition, the user will be provided information on applicable mitigation strategies per device.

Berg, Melanie↗
NASA NTRSDate not supplied

Coherent Architectures for Free-Space Optical Communications

Custom coherent architectures can provide many advantages for FSO communications systems through co-development of integrated photonics, ASIC-or FPGA-based DSP algorithms, and system design to mitigate atmospheric turbulence and reduce pointing requirements.

David J Geisler↗
NASA NTRSDate not supplied

The Solar Neutron TRACking (SONTRAC) Instrument for the Detection of Fast Neutrons

Fast neutrons (energies >0.5 MeV) contribute to the radiation exposure of space hardware and astronaut crew, enable greater understanding of planetary atmospheric and surface compositions and allow unique measurements of solar particle acceleration. Neutrons are challenging to detect and measurements of them typically suffer from high background rates. High energy neutrons (>50 MeV) pose even more challenges, because the traditional double-scatter technique based on a time-of-flight (ToF) measurement. These measurements are challenging due to size constraints on satellites, particularly newer small satellites. The SOlar Neutron TRACking instrument (SONTRAC) is a small satellite neutron detector that utilizes fine-grained scintillating fiber bundles with 1-mm pitch silicon photomultiplier (SiPM) array readout. Signal processing is accomplished with multichannel ASICs. SONTRAC is able to image fast neutron (between 20-200 MeV) scatters in a compact scalable package. We discuss below the numerous applications of this technology and recent progress on the development and performance characteristics of the prototype instrument.

Georgia A de Nolfo↗
NASA NTRS2018

A Novel 3D DRAM Memory Cube Architecture for Space Applications

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.

Yang-Scharlotta, Jean↗
NASA NTRS2020

An embedded planar-foil capacitor material, FPGA based interposer, aimed at improving system performance and reduced board size for space based electronics

This paper presents work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASIC). FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. The developed interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry.

Cheng, Ben↗
NASA NTRS2020

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗
NASA NTRS2022

Single-Event Effect Testing of the PNI RM3100 Magnetometer for Space Applications

The results of a destructive single-event effect susceptibility radiation test of the PNI RM3100 magnetometer sensor, specifically the MagI 2 C ASIC (application-specific integrated circuit) on the sensor board are presented. The sensor is a low-resource commercial off-the-shelf (COTS) magneto-inductive magnetometer. The device was monitored for destructive events and functional interruptions during exposure to a heavy ion beam at the Lawrence Berkeley National Laboratory's 88′′ Cyclotron. The RM3100 did not experience any destructive single-event effects when irradiated to a total fluence of 1.4 × 10 7 cm −2 at an effective linear energy transfer (LET) of 76.7 MeV cm 2 mg −1 while operated at nominal voltage (3.3 V) and elevated temperature (85 ∘C). When these results are combined with previous total ionizing dose tests showing no failures up to 150 kRad (Si), we conclude that the PNI RM3100 is extremely radiation tolerant and can be used in a variety of space environments.

Mark B. Moldwin↗
NASA NTRS2024

EdgeCortix SAKURA-I Machine-Learning, PCIe Accelerator SEE Heavy Ion Test Report

To enable autonomy in space, machine-learning and computer vision applications become invaluable for sensor processing. However, these algorithms are computationally complex and unfeasible for many embedded central processing units (CPUs) and usually require external coprocessors, such as graphics processing units (GPUs) or accelerators specific to the application, including application specific integrated circuits (ASICs). In power-constrained systems, GPUs tend to consume more power than is acceptable (>40W), so lower-power accelerators have shown promise to provide the performance needed under spacecraft constraints. For radiation engineers, developing methodologies that can properly test CPUs, GPUs, and accelerators, and enable comparisons between them remains a necessary complication to solve as the devices become more complex. The methodology in this test aims to be a start in developing a baseline single-event effect (SEE) test for client-device machine learning accelerators. This category of devices do not host their own operating system. This testing campaign is a continuation of a previous 200 MeV proton test performed in January 2024. This report covers two heavy ion tests of the SAKURA-I card: one in April 2024, and one in June 2024. Additional data was needed after the April test due to ion-range issues experienced at higher linear-energy transfers (LETs). These range issues are described in more detail in Section 8. This experiment characterizes SEEs and data error susceptibility of the EdgeCortix SAKURA-I machine-learning accelerator under heavy ions. The device was monitored for single event upsets (SEUs) and single event functional interrupts (SEFIs) at the Lawrence Berkeley National Laboratory’s 88-inch cyclotron. The SAKURA-I board accelerates machine-learning inference applications on a host computer through a PCIex16 connection. For the purposes of devising an end to end automated analysis workflow for this experiment, the YOLO-V5 and SSD300 objection-detection models, and the ResNet-50, EfficientNet, and MobileNetV2 image classification models were used as a representative suite of analytical machine-learning models.

Seth S Roffe↗
NASA NTRS1996

Cascade Helps JPL Explore the Solar System

At Jet Propulsion Laboratory (JPL), we are involved with the unmanned exploration of the solar system. Unmanned probes observe the planet surfaces using radar and optical cameras to take a variety of measurements.

maximum likelihood decoder mcd asic viterbi encodi↗
NASA NTRS1993

A High-Density GaAs Gate Array Chip Set for a Deep Space Digital Receiver

The Jet Propulsin Laboratory (JPL), a division of the California Institute of Technology, performs research, development, and related activities for the National Aeronautics and Space Administration (NASA). JPL is NASA's lead center for unmanned exploration of the solar system and beyond.

designing the ASIC's chip set static timing analyz↗