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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six total institutions performing testing. The outcomes of this internship contribute to Fermilab s mission to advance high-energy physics and support the DOE s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [William Rainey Harper Coll.]↗
DOE OSTI2026

Thermal Studies of CMS High-Granularity Calorimeter (HGCAL) Cassettes for the HL-LHC Upgrade

The CMS High Granularity Calorimeter (HGCAL) is a key endcap upgrade for the High-Luminosity LHC, designed to operate in an environment of extreme radiation and high particle rates. Each HGCAL cassette integrates silicon and scintillator modules, front-end ASICs, and a copper cooling plate that provides both mechanical integrity and thermal coupling using two-phase CO₂ cooling. Stable and uniform temperature control is essential to ensure reliable performance of the front-end electronics and to limit radiation-induced leakage currents in the silicon sensors. We present results from thermal characterization studies of pre-series HGCAL cassettes assembled and tested at Fermilab. Embedded RTD/PT1000 temperature sensors were used to measure gradients across copper cooling plates, module layers, and cassette edges under powering conditions representative of operation. The measured thermal behavior demonstrates effective heat transport through the cassette stack and highlights small but systematic variations correlated with geometry and assembly tolerances. These results validate the cooling performance of HGCAL cassettes.

Wang, Jinglu [Northwestern U.]↗
DOE OSTI2026

Estimating Residual Gas Beam Loss in the BNL AGS Booster:Model, Numerical Tools, and Implications for a Polarimeter Chamber

Beamloss from residual gas scattering is calculated for a storage ring of circumference C = 200m, covering a linear magnetic rigidity ramp from B ρ inj = 1.25Tm to B ρ ext = 9.50Tm over tramp = 1.00s. Three loss mechanisms are considered: nuclear inelastic reactions, single Coulomb scattering beyond the acceptance angle of the machine, and charge-state exchange for heavy ions. Calculations are performed for protons and Au 32+ ions, the latter being the charge state delivered by the EBIS pre-injector into the BNL AGS Booster. At a baseline vacuum of P 0 = 5 × 10 −11 mbar the integrated fractional beam loss over the full ramp is negligible for protons (< 0.001%) and 33.1% for Au 32+ . The impact of a 1m polarimeter section at elevated pressure P s = 5 × 10 −9 mbar is evaluated: the proton loss remains negligible, while the Au 32+ loss rises to 45.1%, establishing the vacuum requirement for the polarimeter chamber. In the present compact approximate model, Au 32+ losses are dominated by charge exchange at injection, while proton losses are dominated by single Coulomb scattering. The design, outgassing budget, pumping strategy, and commissioning sequence for a UHV polarimeter chamber housing silicon detectors and ASICs are described in detail.

43 PARTICLE ACCELERATORS↗
DOE OSTI2026

Developing a GUI for the Robotic Test Stand

The introduction of this poster explains the technology behind DUNE’s far and near detectors and how passing neutrinos generate electrons that drift into a wire grid. I then explain how 3 ASICs manage signals received from electron interception. Next, the poster states how COLDATA chips are undergoing quality control by a Robotic Test Stand using a state machine. I further explained how earlier tests were done via a command line script and the necessity to implement a user-friendly Graphical User Interface with new features a command line can’t implement. For the implementation section, tools and methods for implementation are listed such as Python, tkinter, and GitHub as well as how multithreading and queue implementation was necessary for GUI functionality. Then, I elaborated on the GUIs new features. Finally, I explain how the GUI will be distributed across multiple institutions and future changes planned for the GUI. Photos of the RTS, far detector cave, diagram of anode assembly plane, COLDATA chips, set up tab, result tab, and legacy command line interface are shown.

Gutierrez Villanueva, Jaziel [DuPage Coll.]↗
DOE OSTI2020

MARTA’s (Muon Array with RPC for Tagging Air showers) DAQ system

The successful development of a low-power and standalone DAQ system to be used with RPCs is presented. These will be used to measure the muonic component of cosmic-ray’s air showers. The system includes a front-end, high voltage, detector monitoring and a Central Unit to manage the different components of the system. The front-end is based on the MAROC ASIC coupled to an FPGA respecting the strict demands of field operations in cosmic-ray experiments. Prototypes were produced and deployed, performing as expected. An engineering array will be installed at the Pierre Auger Observatory.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Design and construction of the CMS Outer Tracker for the Phase-2 Upgrade

The High Luminosity LHC (HL-LHC) is expected to deliver an integrated luminosity of $3000-4000\;$fb$^{-1}$ after 10 years of operation with peak instantaneous luminosity reaching about $5-7.5\times10^{34}$cm$^{-2}$s$^{-1}$. During Long Shutdown 3, several components of the CMS detector will undergo major changes, called Phase-2 upgrades, to be able to operate in the challenging environment of the HL-LHC. The current CMS silicon strip tracker has to be replaced with a new detector. The Phase-2 Outer Tracker (OT) will have high radiation tolerance, higher granularity and the capability to handle higher data rates. Another key feature of the OT will be to provide tracking information to the Level-1 trigger, allowing trigger rates to be kept at a sustainable level without sacrificing physics potential. For this, the OT will be made out of modules which have two closely spaced sensors read out by front-end ASICs, which can correlate hits in the two sensors creating short track segments, called stubs. The stubs will be used for tracking in the L1 track finder. In this contribution, the design of the CMS Phase-2 OT, the technological choices and first results with prototype devices are reported.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Low-latency Jet Tagging for HL-LHC Using Transformer Architectures

Transformers are the state-of-the-art model architectures and widely used in application areas of machine learning. However the performance of such architectures is less well explored in the ultra-low latency domains where deployment on FPGAs or ASICs is required. Such domains include the trigger and data acquisition systems of the LHC experiments. We present a transformer-based algorithm for jet tagging built with the HGQ2 framework, which is able to produce a model with heterogeneous bitwidths for fast inference on FPGAs, as required in the trigger systems at the LHC experiments. The bitwidths are acquired during training by minimizing the total bit operations as an additional parameter. By allowing a bitwidth of zero, the model is pruned in-situ during training. Using this quantization-aware approach, our algorithm achieves state-of-the-art performance while also retaining permutation invariance which is a key property for particle physics applications. Due to the strength of transformers in representation learning, our work also serves as a stepping stone for the development of a larger foundation model for trigger applications.

Laatu, Lauri [Imperial Coll., London]↗
DOE OSTI2021

Thin-Entrance Window Process for Soft X-Ray Sensors

New free electron lasers, such as SLAC’s LCLS-II, will provide unique scientific imaging opportunities. In order to fully utilize these facilities, we need to develop detectors with shallow entrance windows that will enable detection of soft x-rays from 250 eV to 1.5 KeV. Achieving adequately shallow entrance windows is challenging because the high temperature anneal needed to activate the dopant also drives the dopant profile deeper, growing the region that is insensitive to soft x-rays. A new microwave annealing technology provides an efficient way to achieve shallow entrance windows in fully depleted high-resistivity silicon sensors. The microwave anneal technique can activate dopants at low substrate temperature, with minimal dopant diffusion, and can be used to fabricate both n-type and p-type entrance windows. SRP and SIMS measurements were used to verify dopant activation with negligible dopant diffusion. We then applied the microwave anneal process to a planar sensor wafer, using the new process to create the backside diode contact. Electrical test of the resulting sensors shows good reverse bias characteristics. The sensors have been bump-bonded to a read-out ASIC and used successfully to measure an Fe-55 x-ray spectrum. Process and device simulations were performed to characterize the quantum efficiency of the entrance window for soft x-rays. This technique is useful for other sensor applications requiring a shallow entrance window, including detectors for UV photons, low energy ions and low energy electrons.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Neural network methods for radiation detectors and imaging

Recent advances in image data proccesing through deep learning allow for new optimization and performance-enhancement schemes for radiation detectors and imaging hardware. This enables radiation experiments, which includes photon sciences in synchrotron and X-ray free electron lasers as a subclass, through data-endowed artificial intelligence. We give an overview of data generation at photon sources, deep learning-based methods for image processing tasks, and hardware solutions for deep learning acceleration. Most existing deep learning approaches are trained offline, typically using large amounts of computational resources. However, once trained, DNNs can achieve fast inference speeds and can be deployed to edge devices. A new trend is edge computing with less energy consumption (hundreds of watts or less) and real-time analysis potential. While popularly used for edge computing, electronic-based hardware accelerators ranging from general purpose processors such as central processing units (CPUs) to application-specific integrated circuits (ASICs) are constantly reaching performance limits in latency, energy consumption, and other physical constraints. These limits give rise to next-generation analog neuromorhpic hardware platforms, such as optical neural networks (ONNs), for high parallel, low latency, and low energy computing to boost deep learning acceleration (LA-UR-23-32395).

edge computing↗
DOE OSTI2023

Equalizing the Pixel Response of the Imaging Photoelectric Polarimeter Onboard the IXPE Mission

The Gas Pixel Detector is a gas detector, sensitive to the polarization of X-rays, currently flying onboard the Imaging X-ray Polarimetry Explorer (IXPE)—the first observatory dedicated to X-ray polarimetry. It detects X-rays and their polarization by imaging the ionization tracks generated by photoelectrons absorbed in the sensitive volume, and then reconstructing the initial direction of the photoelectrons. The primary ionization charge is multiplied and ultimately collected on a finely pixellated ASIC specifically developed for X-ray polarimetry. The signal of individual pixels is processed independently and gain variations can be substantial, of the order of 20%. Such variations need to be equalized to correctly reconstruct the track shape, and therefore its polarization direction. The method to do such equalization is presented here and is based on the comparison between the mean charge of a pixel with respect to the other pixels for equivalent events. The method is shown to finely equalize the response of the detectors onboard IXPE, allowing a better track reconstruction and energy resolution, and can in principle be applied to any imaging detector based on tracks.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

FOS: Computer and information sciences↗
DOE OSTI2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗
DOE OSTI2020

A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Un-fortunately, designing a CGRA for a specific application domain involves enormous software/hardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). Int his paper, we propose AURORA – a software/hardware co-design framework to automatically synthesize optimal CGRA given a set of applications of interest

Tan, Cheng↗
DOE OSTI2021

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis

Domain-specific designs offer greater energy efficiency and performance gain than general-purpose processors. For this reason, modern system-on-chips have a significant portion of their silicon area with custom accelerators. However, designing hardware by hand is laborious and time-consuming, given the large design space and the performance, power, and area constraints that are not realized in the software. Moreover, domain-specific algorithms (e.g., machine learning models) are evolving quickly, challenging the accelerator design further. To address these issues, this paper presents SODA Synthesizer, an automated open-source high-level ML framework to Verilog modular compiler targeting AI/ML Application-Specific Integrated Circuits (ASICs) accelerators. SODA tightly couples the Multi- Level Intermediate Representation (MLIR) compiler infrastructure [24] and open-source HLS approaches. Thus, SODA can support various ML frameworks and algorithms and can perform optimizations that combine specialized architecture templates and conventional HLS to generate the hardware modules. In addition, SODA’s closed-loop design space exploration (DSE) engine allows developers to perform end-to-end design space explorations on different metrics and technology nodes.

Zhang, Jeff↗
DOE OSTI2021

Large scale multi-node simulations of $\mathbb{Z}_2$ gauge theory quantum circuits using Google Cloud Platform

Simulating quantum field theories on a quantum computer is one of the most exciting fundamental physics applications of quantum information science. Dynamical time evolution of quantum fields is a challenge that is beyond the capabilities of classical computing, but it can teach us important lessons about the fundamental fabric of space and time. Whether we may answer scientific questions of interest using near-term quantum computing hardware is an open question that requires a detailed simulation study of quantum noise. Here we present a large scale simulation study powered by a multi-node implementation of qsim using the Google Cloud Platform. We additionally employ newly-developed GPU capabilities in qsim and show how Tensor Processing Units -- Application-specific Integrated Circuits (ASICs) specialized for Machine Learning -- may be used to dramatically speed up the simulation of large quantum circuits. We demonstrate the use of high performance cloud computing for simulating $\mathbb{Z}_2$ quantum field theories on system sizes up to 36 qubits. We find this lattice size is not able to simulate our problem and observable combination with sufficient accuracy, implying more challenging observables of interest for this theory are likely beyond the reach of classical computation using exact circuit simulation.

Gustafson, Erik↗
DOE OSTI2020

The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL

The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Readout of Large Capacitance SiPMs by Weak Coupling to Charge Sensitive Amplifier

Large area and large capacitance silicon photomultiplier (SiPM) arrays are employed to collect scintillation light in noble liquid time projection chambers (TPC) such as DarkSide, nEXO, MEGII, protoDUNE and DUNE. Light readout using ASICs designed for operation in noble liquids is a solution for large meter-scale photon detectors. However, conventional readout requires a high voltage decoupling capacitor larger than SiPM capacitance (in the range of tens of nF) to achieve full charge transfer to the preamplifier. Here, we demonstrate a readout concept by weakly coupling (via a capacitor lower by an order of magnitude than SiPM capacitance) to a charge sensitive amplifier, LArASIC in this case, without any loss in the signal to noise ratio (S/N). The single-photoelectron detection, signal-to-noise ratio, timing resolution, and coincidence detection are experimentally characterized.

47 OTHER INSTRUMENTATION↗