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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12

Using Integer Clocks to Verify the Timing-Sync Sensor Network Protocol

We use the UPPAAL model checker for Timed Automata to verify the Timing-Sync time-synchronization protocol for sensor networks (TPSN). The TPSN protocol seeks to provide network-wide synchronization of the distributed clocks in a sensor network. Clock-synchronization algorithms for sensor networks such as TPSN must be able to perform arithmetic on clock values to calculate clock drift and network propagation delays. They must be able to read the value of a local clock and assign it to another local clock. Such operations are not directly supported by the theory of Timed Automata. To overcome this formal-modeling obstacle, we augment the UPPAAL specification language with the integer clock derived type. Integer clocks, which are essentially integer variables that are periodically incremented by a global pulse generator, greatly facilitate the encoding of the operations required to synchronize clocks as in the TPSN protocol. With this integer-clock-based model of TPSN in hand, we use UPPAAL to verify that the protocol achieves network-wide time synchronization and is devoid of deadlock. We also use the UPPAAL Tracer tool to illustrate how integer clocks can be used to capture clock drift and resynchronization during protocol execution

Huang, Xiaowan↗

Global synchronization of parallel processors using clock pulse width modulation

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

97 MATHEMATICS AND COMPUTING↗

Methods and systems of synchronizer selection

A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

42 ENGINEERING↗

Real-time simulation clock

The invention is a clock for synchronizing operations within a high-speed, distributed data processing network. The clock is actually a distributed system comprising a central clock and multiple site clock interface units (SCIUs) which are connected by means of a fiber optic star network and which operate under control of separate clock software. The presently preferred embodiment is a part of the flight simulation system now in current use at the NASA Langley Research Center.

Bennington, Donald R.↗

Precise time dissemination via portable atomic clocks

The most precise operational method of time dissemination over long distances presently available to the Precise Time and Time Interval (PTTI) community of users is by means of portable atomic clocks. The Global Positioning System (GPS), the latest system showing promise of replacing portable clocks for global PTTI dissemination, was evaluated. Although GPS has the technical capability of providing superior world-wide dissemination, the question of present cost and future accessibility may require a continued reliance on portable clocks for a number of years. For these reasons a study of portable clock operations as they are carried out today was made. The portable clock system that was utilized by the U.S. Naval Observatory (NAVOBSY) in the global synchronization of clocks over the past 17 years is described and the concepts on which it is based are explained. Some of its capabilities and limitations are also discussed.

Putkovich, K.↗

Satellite Time- and Frequency-Transfer System

Time synchronized at distant points within nanosecond. Report describes satellite-borne time-and frequency-transfer system proposed for synchronization of clocks at stations around Earth. Orbiting hydrogen-maser clock and frequency standard communicate by microwave links with Earth stations using hydrogen masers as local clocks. Pulsed-laser time-transfer sub-system also operated concurrently, either synchronized or unsynchronized with microwave subsystems.

Vessot, R. F. C.↗

Synchronized electric meter having an atomic clock

Smart electric meters configured to perform fast, time-synchronized electrical energy measurements at the consumer-level are disclosed herein. In some embodiments, a smart electric meter includes circuitry configured to measure an electrical value at a location of an end user in a power system. The smart electric meter can further include an atomic clock configured to output a timing signal, and a controller configured to receive (a) the measured electrical value from the circuitry and (b) the timing signal from the atomic clock. The controller can further (a) process the electrical value to generate meter data and (b) generate a time tag based on the timing signal. Then, the controller can associate the time tag with the meter data to generate time-tagged meter data.

Min, Liang↗

About time

Time has historically been a measure of progress of recurrent physical processes. Coordination of future actions, prediction of future events, and assigning order to events are three practical reasons for implementing clocks and signalling mechanisms. In large networks of computers, these needs lead to the problem of synchronizing the clocks throughout the network. Recent methods allow this to be done in large networks with precision around 1 millisecond despite mean message exchange times near 5 milliseconds. These methods are discussed.

Denning, Peter J.↗

Servo control and data synchronization study

Magnetic tape recorder-reproducer to accept data pulses at varying rates, record data at constant rate, and retrieve recorded data at rate synchronized to external clock

SYNCHRONIZATION↗

Review of available synchronization and time distribution techniques

The methods of synchronizing precision clocks will be reviewed placing particular attention to the simpler techniques, their accuracies, and the approximate cost of equipment. The more exotic methods of synchronization are discussed in lesser detail. The synchronization techniques that will be covered will include satellite dissemination, communication and navigation transmissions via VLF, LF, HF, UHF and microwave as well as commercial and armed forces television. Portable clock trips will also be discussed.

Hall, R. G.↗

General Solution for Theoretical Packet Data Loss Rate

Communications systems which transfer blocks ("frames") of data must use a marker ("frame synchronization pattern") for identifying where a block begins. A technique ("frame synchronization strategy") is used to locate the start of each frame and maintain synchronization as additional blocks are processed. A device which strips out the frame synchronization pattern [FSP] and provides an "end of frame" pulse is called a frame synchronizer. As clock and data errors are introduced into the system, the start-of-block marker becomes displaced and/or corrupted. The capability of the frame synchronizer to stay locked to the pattern under these conditions is a figure of merit for the frame synchronization strategy. It is important to select a strategy which will stay locked nearly all the time at bit error rates where the data is usable. ("Bit error rate" [BER] is the fraction of binary bits which are inverted by passage through a communication system.) The fraction of frames that are discarded because the frame synchronizer is not locked is called "Percent Data Loss" or "Packet Data Loss rate" [PDL]. A general approach for accurately predicting PDL given BER was developed in Theoretical Percent Data Loss Calculation and Measurement Accuracy, T. P. Kelly, LESC-30554, December 1992. Kelly gave a solution in terms of matrix equations, and only addressed "level" channel encoding. This paper goes on to give a closed-form polynomial solution for the most common class of frame synchronizer strategies, and will also address "mark" and "space" (differential) channel encoding, and burst error environments. The paper is divided into four sections and follows a logically ordered presentation, with results developed before they are evaluated. However, most readers will derive the greatest benefit from this paper by treating the results as reference material. The result developed for differential encoding can be extended to other applications (like block codes) where the probability is needed that a block contains only a certain number of errors.

Lansdowne, Chatwin↗

An evaluation of the state of time synchronization on leadership class supercomputers

We present a detailed examination of time agreement characteristics for nodes within extreme-scale parallel computers. Using a software tool we introduce in this paper, we quantify attributes of clock skew among nodes in three representative high-performance computers sited at three national laboratories. Our measurements detail the statistical properties of time agreement among nodes and how time agreement drifts over typical application execution durations. We discuss the implications of our measurements, why the current state of the field is inadequate, and propose strategies to address observed shortcomings.

97 MATHEMATICS AND COMPUTING↗

Timing and synchronization of the DUNE neutrino detector

The DUNE neutrino experiment far detector has a fiducial mass of 40 kt. The O(1 M) readout channels are distributed over the 4 x 10kt modules and need to be synchronized to O(10 ns) with a reliable, simple, affordable system. For the majority of channels a simple DC-balanced protocol is used, with clock and synchronization information encoded on the same fibre. The remaining channels use “White Rabbit” (IEEE-1588). Small scale tests show a timing jitter of <100 ps. The DUNE timing system has been successfully prototyped at the ProtoDUNE-SP detector at CERN.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Formal verification of algorithms for critical systems

We describe our experience with formal, machine-checked verification of algorithms for critical applications, concentrating on a Byzantine fault-tolerant algorithm for synchronizing the clocks in the replicated computers of a digital flight control system. First, we explain the problems encountered in unsynchronized systems and the necessity, and criticality, of fault-tolerant synchronization. We give an overview of one such algorithm, and of the arguments for its correctness. Next, we describe a verification of the algorithm that we performed using our EHDM system for formal specification and verification. We indicate the errors we found in the published analysis of the algorithm, and other benefits that we derived from the verification. Based on our experience, we derive some key requirements for a formal specification and verification system adequate to the task of verifying algorithms of the type considered. Finally, we summarize our conclusions regarding the benefits of formal verification in this domain, and the capabilities required of verification systems in order to realize those benefits.

Rushby, John M.↗

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Central and peripheral regulation of feeding and nutrition by the mammalian circadian clock: implications for nutrition during manned space flight

Circadian clocks have evolved to predict and coordinate physiologic processes with the rhythmic environment on Earth. Space studies in non-human primates and humans have suggested that this clock persists in its rhythmicity in space but that its function is altered significantly in long-term space flight. Under normal circumstances, the clock is synchronized by the light-dark cycle via the retinohypothalamic tract and the suprachiasmatic nucleus. It is also entrained by restricted feeding regimes via a suprachiasmatic nucleus-independent circadian oscillator. The site of this suboscillator (or oscillators) is not known, but new evidence has suggested that peripheral tissues in the liver and viscera may express circadian clock function when forced to do so by restricted feeding schedules or other homeostatic disruptions. New research on the role of the circadian clock in the control of feeding on Earth and in space is warranted.

NASA Discipline Regulatory Physiology↗