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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

A hybrid M-algorithm/sequential decoder for convolutional and trellis codes

The Viterbi Algorithm (VA) is optimum in the sense of being maximum likelihood for decoding codes with a trellis structure. However, since the VA is in fact an exhaustive search of the code trellis, the complexity of the VA grows exponentially with the constraint length upsilon. This limits its application to codes with small values of upsilon and relatively modest coding gains. The M-Algorithm (MA) is a limited search scheme which carries forward M paths in the trellis, all of the same length. All successors of the M paths are extended at the next trellis depth, and all but the best M of these are dropped. Since a limited search convolutional decoder will flounder indefinitely if one of the paths in storage is not the correct one, the data are usually transmitted in blocks. It has been shown that the performance of the MA approaches the VA at high signal to noise ratios (SNR's) with an M which is far less than the 2 sup upsilon states in the full trellis. Thus the MA can be used with larger values of upsilon, making larger coding gains possible at high SNR's. However, it still requires a relatively large fixed computational effort to achieve good performance.

Wang, Fu-Quan↗
NASA NTRS1990

Study of a co-designed decision feedback equalizer, deinterleaver, and decoder

A technique that promises better quality data from band limited channels at lower received power in digital transmission systems is presented. Data transmission, in such systems often suffers from intersymbol interference (ISI) and noise. Two separate techniques, channel coding and equalization, have caused considerable advances in the state of communication systems and both concern themselves with removing the undesired effects of a communication channel. Equalizers mitigate the ISI whereas coding schemes are used to incorporate error-correction. In the past, most of the research in these two areas has been carried out separately. However, the individual techniques have strengths and weaknesses that are complementary in many applications: an integrated approach realizes gains in excess to that of a simple juxtaposition. Coding schemes have been successfully used in cascade with linear equalizers which in the absence of ISI provide excellent performance. However, when both ISI and the noise level are relatively high, nonlinear receivers like the decision feedback equalizer (DFE) perform better. The DFE has its drawbacks: it suffers from error propagation. The technique presented here takes advantage of interleaving to integrate the two approaches so that the error propagation in DFE can be reduced with the help of error correction provided by the decoder. The results of simulations carried out for both, binary, and non-binary, channels confirm that significant gain can be obtained by codesigning equalizer and decoder. Although, systems with time-invariant channels and simple DFE having linear filters were looked into, the technique is fairly general and can easily be modified for more sophisticated equalizers to obtain even larger gains.

Peile, Robert E.↗
NASA NTRS1992

VLSI architecture for a Reed-Solomon decoder

A basic single-chip building block for a Reed-Solomon (RS) decoder system is partitioned into a plurality of sections, the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10 and 8 bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10 and 8 bit operation.

Hsu, In-Shek↗
NASA NTRS1992

A VLSI design for a trace-back Viterbi decoder

A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

Truong, T. K.↗
NASA NTRS1992

On the decoder error probability of block codes

By using coding and combinational techniques, an explicit formula is derived which enumerates the complete weight distribution of decodable words of block codes using partially known weight distributions. Also an approximation formula for nonbinary block codes is obtained. These results in turn give exact and approximate expressions for the decoder error probability PE(u) of block codes.

Cheung, Kar-Ming↗
NASA NTRS1992

The algebraic decoding of the (41, 21, 9) quadratic residue code

A new algebraic approach for decoding the quadratic residue (QR) codes, in particular the (41, 21, 9) QR code is presented. The key ideas behind this decoding technique are a systematic application of the Sylvester resultant method to the Newton identities associated with the code syndromes to find the error-locator polynomial, and next a method for determining error locations by solving certain quadratic, cubic and quartic equations over GF(2 exp m) in a new way which uses Zech's logarithms for the arithmetic. The algorithms developed here are suitable for implementation in a programmable microprocessor or special-purpose VLSI chip. It is expected that the algebraic methods developed here can apply generally to other codes such as the BCH and Reed-Solomon codes.

Reed, Irving S.↗
NASA NTRS1993

Add/Compare/Select Circuit For Rapid Decoding

Prototype decoding system operates at 200 Mb/s. ACS (add/compare/select) gate array is highly integrated emitter-coupled-logic circuit implementing arithmetic operations essential to Viterbi decoding of convolutionally encoded data signals. Principal advantage of circuit is speed. Operates as single unit performing eight additions and finds minimum of eight sums, or operates as two independent units, each performing four additions and finding minimum of four sums. Flexibility enables application to variety of different codes. Includes built-in self-testing circuitry, enabling unit to be tested at full speed with help of only simple test fixture.

Budinger, James M.↗
NASA NTRS1993

Soft decoding a self-dual (48, 24; 12) code

A self-dual (48,24;12) code comes from restricting a binary cyclic (63,18;36) code to a 6 x 7 matrix, adding an eighth all-zero column, and then adjoining six dimensions to this extended 6 x 8 matrix. These six dimensions are generated by linear combinations of row permutations of a 6 x 8 matrix of weight 12, whose sums of rows and columns add to one. A soft decoding using these properties and approximating maximum likelihood is presented here. This is preliminary to a possible soft decoding of the box (72,36;15) code that promises a 7.7-dB theoretical coding under maximum likelihood.

Solomon, G.↗
NASA NTRS1994

Real-Time Reed-Solomon Decoder

Generic Reed-Solomon decoder fast enough to correct errors in real time in practical applications designed to be implemented in fewer and smaller very-large-scale integrated, VLSI, circuit chips. Configured to operate in pipelined manner. One outstanding aspect of decoder design is that Euclid multiplier and divider modules contain Galoisfield multipliers configured as combinational-logic cells. Operates at speeds greater than older multipliers. Cellular configuration highly regular and requires little interconnection area, making it ideal for implementation in extraordinarily dense VLSI circuitry. Flight electronics single chip version of this technology implemented and available.

Maki, Gary K.↗
NASA NTRS1993

High-speed Viterbi decoding with overlapping code sequences

The Viterbi Algorithm for decoding convolutional codes and Trellis Coded Modulation is suited to VLSI implementation but contains a feedback loop which limits the speed of pipelined architecture. The feedback loop is circumvented by decoding independent sequences simultaneously, resulting in a 5-9 fold speed-up with a two-fold hardware expansion.

Ross, Michael D.↗
NASA NTRS1993

Separable concatenated codes with iterative map decoding for Rician fading channels

Very efficient signalling in radio channels requires the design of very powerful codes having special structure suitable for practical decoding schemes. In this paper, powerful codes are obtained by combining comparatively simple convolutional codes to form multi-tiered 'separable' convolutional codes. The decoding of these codes, using separable symbol-by-symbol maximum a posteriori (MAP) 'filters', is described. It is known that this approach yields impressive results in non-fading additive white Gaussian noise channels. Interleaving is an inherent part of the code construction, and consequently, these codes are well suited for fading channel communications. Here, simulation results for communications over Rician fading channels are presented to support this claim.

Lodge, J. H.↗
NASA NTRS1994

Decoder synchronization for deep space missions

The Consultative Committee for Space Data Standards (CCSDS) recommends that space communication links employ a concatenated, error-correcting, channel-coding system in which the inner code is a convolutional (7,1/2) code and the outer code is a (255,223) Reed-Solomon code. The traditional implementation is to perform the node synchronization for the Viterbi decoder and the frame synchronization for the Reed-Solomon decoder as separate, sequential operations. This article discusses a unified synchronization technique that is required for deep space missions that have data rates and signal-to-noise ratios (SNR's) that are extremely low. This technique combines frame synchronization in the bit and symbol domains and traditional accumulated-metric growth techniques to establish a joint frame and node synchronization. A variation on this technique is used for the Galileo spacecraft on its Jupiter-bound mission.

Statman, J. I.↗
NASA NTRS1994

Issues in the development of a 10 MBPS K=15 Viterbi decoder

The NMSU Telemetry Center, in collaboration with the NASA Microelectronics Center (MRC) at UNM, has completed a study of the feasibility of building a constraint length 15, rate 1/2 Viterbi Decoder (or BVD) to operate at a rate of 10 Mbps. The BVD, if built, would make TDRSS more accessible to all users, small satellites in particular, by providing an additional 2 dB of link margin, relative to the use of the standard constraint length 7 decoder. The study included the following: review of the 1 Mbps BVD built by the Jet Propulsion Laboratory (JPL), currently the only BVD in existence; development of Specifications for the basic processing unit of the BVD (MRC); analytical Determination of performance of large constraint length convolutional codes; investigation of the impact of processor design on the overall system design; and two feasible packaging technologies, proposed by Cincinnati Electronics of Ohio. It was concluded that while the construction of the BVD is feasible, it will require the most advanced packaging technology currently available, and that the project would be best accomplished in an industrial facility. While the size, complexity, and power requirements of the BVD will be extreme, these will impact only the ground station. The spacecraft will incur a minor change in the encoder design, and the increased coding gain will allow a satellite to operate with a smaller antenna.

Osborne, William P.↗
NASA NTRS1995

Joint Synchronization Of Viterbi And Reed-Solomon Decoders

Synchronization times reduced to reduce loss of data. Scheme for decoding received doubly encoded binary-data signal provides for joint synchronization of two decoders. Applies to concatenated error-correcting channel coding communication system in which, at transmitter, data first encoded by interleaved Reed-Solomon code (block code), then by convolutional code.

Statman, Joseph I.↗
NASA NTRS1996

Architecture and implementation considerations of a high-speed Viterbi decoder for a Reed-Muller subcode

The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.

Lin, Shu↗
NASA NTRS1996

Soft-decision decoding techniques for linear block codes and their error performance analysis

The first paper presents a new minimum-weight trellis-based soft-decision iterative decoding algorithm for binary linear block codes. The second paper derives an upper bound on the probability of block error for multilevel concatenated codes (MLCC). The bound evaluates difference in performance for different decompositions of some codes. The third paper investigates the bit error probability code for maximum likelihood decoding of binary linear codes. The fourth and final paper included in this report is concerns itself with the construction of multilevel concatenated block modulation codes using a multilevel concatenation scheme for the frequency non-selective Rayleigh fading channel.

Lin, Shu↗
NASA NTRS1996

Multichannel Error Correction Code Decoder

NASA Lewis Research Center's Digital Systems Technology Branch has an ongoing program in modulation, coding, onboard processing, and switching. Recently, NASA completed a project to incorporate a time-shared decoder into the very-small-aperture terminal (VSAT) onboard-processing mesh architecture. The primary goal was to demonstrate a time-shared decoder for a regenerative satellite that uses asynchronous, frequency-division multiple access (FDMA) uplink channels, thereby identifying hardware and power requirements and fault-tolerant issues that would have to be addressed in a operational system. A secondary goal was to integrate and test, in a system environment, two NASA-sponsored, proof-of-concept hardware deliverables: the Harris Corp. high-speed Bose Chaudhuri-Hocquenghem (BCH) codec and the TRW multichannel demultiplexer/demodulator (MCDD). A beneficial byproduct of this project was the development of flexible, multichannel-uplink signal-generation equipment.

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