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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Probing the Atomic Scale Mechanisms of Time Dependent Dielectric Breakdown in Si/SiO 2 MOSFETs (June 2022)

Here we report on an atomic-scale study of trap generation in the initial/intermediate stages of time-dependent dielectric breakdown (TDDB) in high-field stressed (100) Si/SiO2 MOSFETs using two powerful analytical techniques: electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR). We find the dominant EDMR-sensitive traps generated throughout the majority of the TDDB process to be silicon dangling bonds at the (100) Si/SiO2 interface (Pb0 and Pb1 centers) for both the spin-dependent recombination (SDR) and trap-assisted tunneling (SDTAT) processes. We find this generation to be linked to both changes in the calculated interface state densities as well as changes in the NZFMR spectra for recombination events at the interface, indicating a redistribution of mobile magnetic nuclei which we conclude could only be due to the redistribution of hydrogen at the interface. Additionally, we observe the generation of traps known as E’ centers in EDMR measurements at lower experimental temperatures via SDR measurements at the interface. Our work strongly suggests the involvement of a rate-limiting step in the tunneling process between the silicon dangling bonds generated at the interface and the ones generated throughout the oxide.

36 MATERIALS SCIENCE↗
DOE OSTI2022

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗
DOE OSTI2021

Impact of Surface Recombination on Single-Event Charge Collection in an SOI Technology

Semiconductor–insulator interfaces play an important role in the reliability of integrated devices; however, the impact of these interfaces on the physical mechanisms related to single-event effects has not been previously reported. We present experimental data that demonstrate that single-event charge collection can be impacted by changes in interface quality. The experimental data, combined with simulations, show that single-event response may depend on surface recombination at interface defects. The effect depends on strike location and increases with increasing linear energy transfer (LET). Surface recombination can affect single-event charge collection for interfaces with a surface recombination velocity (SRV) of 1000 cm/s and is a dominant charge collection mechanism with SRV >10 5 cm/s.

42 ENGINEERING↗
DOE OSTI2021

Characterization of a Small-Scale Prototype Detector With Wide Dynamic Range for Time-Resolved High-Energy X-Ray Applications

We present characterization measurements of a fast-framing, wide-dynamic-range x-ray area detector intended for high-energy applications (≥20 keV photons). The MM-PAD-2.1 combines an integrating pixel front-end with a charge-removal mechanism to extend the maximum measurable signal to > 107 20-keV ph/pixel/frame. The charge-removal mechanism is dead-time-less (i.e., incoming signal continues to be integrated by the front-end while charge removal is taking place) up to an incoming photon rate of > 109 20-keV ph/pix/s. A 16×16 pixel prototype was fabricated and characterized using both laboratory and synchrotron x-ray sources, allowing for measurements from single-photon to high-flux conditions. High-flux measurements show linear performance up to ~1010 ph/s in a spot spanning approximately 2×1.5 pixels (FWHM). The onset of temporary radiation damage in the detector was observed during these measurements, manifesting as failure of the digital readout from the detector. These effects were seen to reverse after annealing at 30° C for several hours.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Quantum computing in power systems

Electric power systems provide the backbone of modern industrial societies. Enabling scalable grid analytics is the keystone to successfully operating large transmission and distribution systems. However, today's power systems are suffering from ever-increasing computational burdens in sustaining the expanding communities and deep integration of renewable energy resources, as well as managing huge volumes of data accordingly. These unprecedented challenges call for transformative analytics to support the resilient operations of power systems. Recently, the explosive growth of quantum computing techniques has ignited new hopes of revolutionizing power system computations. Quantum computing harnesses quantum mechanisms to solve traditionally intractable computational problems, which may lead to ultra-scalable and efficient power grid analytics. This paper reviews the newly emerging application of quantum computing techniques in power systems. We present a comprehensive overview of existing quantum-engineered power analytics from different operation perspectives, including static analysis, transient analysis, stochastic analysis, optimization, stability, and control. We thoroughly discuss the related quantum algorithms, their benefits and limitations, hardware implementations, and recommended practices. We also review the quantum networking techniques to ensure secure communication of power systems in the quantum era. Finally, we discuss challenges and future research directions. This paper will hopefully stimulate increasing attention to the development of quantum-engineered smart grids.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1987

Diagnostic emulation: Implementation and user's guide

The Diagnostic Emulation Technique was developed within the System Validation Methods Branch as a part of the development of methods for the analysis of the reliability of highly reliable, fault tolerant digital avionics systems. This is a general technique which allows for the emulation of a digital hardware system. The technique is general in the sense that it is completely independent of the particular target hardware which is being emulated. Parts of the system are described and emulated at the logic or gate level, while other parts of the system are described and emulated at the functional level. This algorithm allows for the insertion of faults into the system, and for the observation of the response of the system to these faults. This allows for controlled and accelerated testing of system reaction to hardware failures in the target machine. This document describes in detail how the algorithm was implemented at NASA Langley Research Center and gives instructions for using the system.

Becher, Bernice↗
NASA NTRS1989

Characterization of the faulted behavior of digital computers and fault tolerant systems

A development status evaluation is presented for efforts conducted at NASA-Langley since 1977, toward the characterization of the latent fault in digital fault-tolerant systems. Attention is given to the practical, high speed, generalized gate-level logic system simulator developed, as well as to the validation methodology used for the simulator, on the basis of faultable software and hardware simulations employing a prototype MIL-STD-1750A processor. After validation, latency tests will be performed.

Bavuso, Salvatore J.↗
NASA NTRS2018

Using GPS Receivers 1PPS Output to Verify Time Stamp Accuracy and Measure Propagation Delay

A simple Pulse Overlay (PO) circuit using a logic OR gate was developed to overlay a precise leading edge 1 Pulse Per Second (1PPS) time reference marker from a GPS receiver onto a Non-Return -to- Zero-Level (NRZ-L) Pulse Code Modulation (PCM) telemetry data stream to validate time stamp accuracy and measure propagation delay (PD) in telemetry equipment.

telemetry↗
NASA NTRS2018

Using GPS Receiver 1PPS Output to Verify Time Stamp Accuracy and Measure Propagation Delay

A simple pulse overlay circuit using a logic OR gate was developed to overlay a precise leading edge 1 pulse per second time reference marker from a global positioning system receiver onto a non-return -to- zero-level pulse code modulation telemetry data stream to validate time stamp accuracy and measure propagation delay in telemetry equipment. A pulse overlay (PO) circuit was designed to produce a time reference marker within a pulse code modulation (PCM) telemetry data stream that was recorded and analyzed to validate an IRIG Standard 106-17 Chapter 10 recorder’s time stamp accuracy [1]. A manufacturer of a newly purchased Chapter 10 recorder claimed the time stamp accuracy to be better than 10 microseconds (μs) with only IRIG-B120 (IRIG-B) input and better than 1 μs with IRIG-B and one pulse per second (1PPS) inputs. The PO circuit and a Chapter 10 recorder test setup were used to verify the vendor’s data-time synchronization claims and to justify infrastructure upgrade costs to connect additional cables to each purchased recorder. The circuit was also used to measure the propagation delay (PD) of a long distance Telemetry multiplexer/demultiplexer telecommunication system which the manufacturer did not provide a PD specification. Using the one pulse per second time reference marker of the global positioning system receiver and the pulse overlay circuit to overlay the one pulse per second variable pulse width signal into a pulse code modulation telemetry stream provided an excellent means to validate time stamp accuracy within a Chapter 10 recorder and to measure propagation delays within a normal telemetry operating environment. The positive results from the Chapter 10 recorder tests validated the vendor’s claims and justified the implementation to add the one pulse per second signal to the range Chapter 10 recorders. The pulse overlay circuit and test setups defined in this paper can easily be used to measure other telemetry equipment.

Knudtson, Kevin↗
NASA NTRS2019

Using GPS Receiver 1PPS Output to Verify Time Stamp Accuracy and Measure Propagation Delay

A simple pulse overlay circuit using a logic OR gate was developed to overlay a precise leading edge 1 pulse per second time reference marker from a global positioning system receiver onto a non-return -to- zero-level pulse code modulation telemetry data stream to validate time stamp accuracy and measure propagation delay in telemetry equipment.

time stamp offset↗
DOE OSTI2023

Logical quantum processor based on reconfigurable atom arrays

Suppressing errors is the central challenge for useful quantum computing, requiring quantum error correction (QEC) for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays, our system combines high two-qubit gate fidelities, arbitrary connectivity, as well as fully programmable single-qubit rotations and mid-circuit readout. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code distance from d = 3 to d = 7, preparation of colour-code qubits with break-even fidelities, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks, we realize computationally complex sampling circuits with up to 48 logical qubits entangled with hypercube connectivity with 228 logical two-qubit gates and 48 logical CCZ gates. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2026

Fault-tolerant resource comparison of qudit and qubit encodings for diagonal quadratic operators

Finite local Hilbert-space truncations arise naturally in quantum simulations of lattice field theories and motivate qudit encodings, but their fault-tolerant advantage over qubit encodings remains unclear. We compare the non-Clifford cost of implementing quadratic diagonal evolutions, exemplified by 𝑈 = 𝑒$^{−𝑖⁢𝑡⁢𝜙^2_𝑥}$ in a uniform field-amplitude discretization of a real scalar field, using either one logical 𝑑-level qudit or 𝑛 𝑏 = ⌈log 2⁡ 𝑑⌉ logical qubits. We analyze two standard settings: product-formula simulation and linear combination of unitaries (LCU) per block encoding, taking the resource metric to be the number of non-Clifford gates after synthesis into a discrete logical gate set. Because tight synthesis bounds for general single-qudit rotations are not known, we express the qudit constructions in terms of embedded two-level SU⁡(2) rotations and derive explicit finite-𝑑 break-even conditions for their synthesis cost; these serve as compiler targets for when qudit encodings can outperform the qubit baseline. Within the constructive models studied here, product-formula implementations would require an exponentially stronger per-primitive synthesis advantage for qudits to win asymptotically, while in the LCU setting the qubit encoding is asymptotically cheaper in 𝑑. Nevertheless, the finite-𝑑 threshold analysis identifies low-dimensional regions in which qudits can yield meaningful constant-factor savings, particularly for LCU-based implementations. As a secondary analysis of the LCU construction, we use an idealized negligible-overhead qubit-qudit code-switching model to give an absolute 𝑇-count comparison and reinterpret the savings as an allowable per-switch overhead budget.

Godwood, Samuel [Univ. of Liverpool (United Kingdo↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗