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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.
A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.
The tunneling characteristics of Cr/SiO2/Si structures in the thickness range from 23 to 34 A are reported. The E-kappa dependence in the energy range extending 3.5 eV below the oxide conduction band is determined by the thickness dependence to be approximately of the Franz form with an effective mass ratio of 0.42. Tunneling into the indirect conduction band of silicon is reduced by a thickness-independent factor which decreases approximately exponentially with the energy below the direct band edge.
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An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
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It is pointed out that the reported measurements are useful in a study of interface charge distributions. Measurements of surface-state density at the SiO2 interface given information concerning the effect of the layer thickness on the flat-band interface charge. Other measurements provide data for a determination of the silicon-silica flat-band interface charge, the metal-silica interface charge, and the difference in barrier energies at the interfaces. Measurements of Fowler-Nordheim currents as a function of oxide thickness can be used for the determination of charge distribution in the area next to the metal-silica interface. The investigation shows that the silicon-silica interface is independent of thickness down to thicknesses as low as 40 A.
Method allows flatband voltage measurement of capacitors to be taken quickly and precisely while capacitor is subject to desired conditions.
Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.
The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.
The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.
The trapping parameters for holes, and for electrons in the presence of trapped holes, have been measured from a set of wafers with different oxide thickness processed under controlled conditions. The trap cross-sections and densities indicate at least three trap species, including an interfacial species, a dominant bulk species which is determined to tail off from the silicon interface, and a third, lower density bulk species that is distributed throughout the oxide.
Quantitative model for MOC breakdown is derived and correlated with experiments.
Electron injection technique serves as powerful probe of trapped hole distribution after irradiation because it was determined that electrons only annihilate trapped holes. Other effects, such as other electron traps and interface state generation, are negligible in injection range used. Trap cross sections and densities indicate at least three trap species; interfacial species, dominant bulk species determined to tail off from silicon interface, and lower density and cross section species that may be distributed throughout bulk of oxide.
Thin sputter deposited MoS2 films in the 2000 to 6000 A thickness range have shown excellent lubricating properties, when sputtering parameters and substrate conditions are properly selected and precisely controlled. The lubricating properties of sputtered MoS2 films are strongly influenced by their crystalline-amorphous structure, morphology and composition. The coefficient of friction can range from 0.04 which is effective lubrication to 0.4 which reflects an absence of lubricating properties. Visual screening and slight wiping of the as-sputtered MoS2 film can identify the integrity of the film. An acceptable film displays a black-sooty surface appearance whereas an unacceptable film has a highly reflective, gray surface and the film is hard and brittle.
Lead chalcogenide photoresistors integrated with FET amplifiers. Circuit combines voltage divider containing lead chalcogenide photoresistor with FET source follower. Source and drain of FET p-doped regions in underlying n-type silicon wafer. All other structures formed at or deposited above original surface plane of wafer.
Low temperature operation of micron and submicron size Si MOSFETs (metal-oxide-semiconductor field-effect-transistors) results in their improved device characteristics. Various low temperature device properties such as increase in mobility, shift in the theshold voltage, increased reliability, etc., were considered. Other device characteristics such as the subthreshold behavior, delay times and miniaturization at low temperatures are discussed. Discussion includes presenting experimental results along with physical models explaining the observed effects.
The goal was to design single-chip lowpass filters with constant group delay in the pass band and 60 dB minimum attenuation in the stop band. The desired 3 dB frequencies are (in Hertz) 2.5, 5, 10, 20, 40, 80, 160, and 320. A filter class that satisfies the constant delay (linear phase) requirement while providing quite a narrow transition band is the Bessel-Chebyshev filters. It was found that the 7th order Bessel-Chebyshev response satisfied the requirement of the filter.